INTEGRATED DEVICE INCORPORATING LOW-VOLTAGE COMPONENTS AND POWER COMPONENTS, AND PROCESS FOR MANUFACTURING SUCH DEVICE

• US 20110018068A1
• Filed: 07/20/2010
• Published: 01/27/2011
• Est. Priority Date: 07/21/2009
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: DEPETRO, Riccardo, MANZINI, Stefano
• Granted Patent: US 8,975,723 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66696 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

An integrated device includes: a semiconductor body having a first, depressed, portion and second portions which project from the first portion; a STI structure, extending on the first portion of the semiconductor body, which delimits laterally the second portions and has a face adjacent to a surface of the first portion; low-voltage CMOS components, housed in the second portions, in a first region of the semiconductor body; and a power component, in a second region of the semiconductor body. The power component has at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, connected to the conduction region and traversing the STI structure in a direction perpendicular to the surface of the first portion of the semiconductor body.

Claims

1. Integrated device comprising:

a semiconductor body having a depressed first portion and second portions projecting from the first portion;

an STI insulation structure, extending on the first portion of the semiconductor body, laterally delimiting the second portions of the semiconductor body and having a face adjacent to a surface of the first portion of the semiconductor body;

low-voltage CMOS components, accommodated in the second portions, in a first region of the semiconductor body; and

a power component, in a second region of the semiconductor body;

wherein the power component comprises at least one conduction region, formed in the first portion of the semiconductor body, and a conduction contact, connected to the conduction region and crossing the STI insulation structure perpendicularly to the surface of the first portion of the semiconductor body.

2. Device according to claim 1, wherein the conduction region is formed below the STI insulation structure.

3. Device according to claim 1, wherein the STI insulation structure has an aperture crossed by the conduction contact.

4. Device according to claim 3, wherein the aperture is delimited by walls having a slope comprised between 20°

and 70°

.

5. Device according to claim 1, wherein the conduction region is a source region.

6. Device according to claim 5, comprising a body region, formed in the first portion of the semiconductor body and accommodating the conduction region.

7. Device according to claim 6, comprising a gate region, arranged in part in the apertured extending above a junction region of the semiconductor body adjacent to the body region, above a channel region defined by a portion of the body region comprised between the junction region and the conduction region, and above part of the conduction region.

8. Device according to claim 7, wherein the gate region extends in part above the STI insulation structure.

9. Device according to claim 1, wherein the semiconductor body comprises at least a third portion projecting from the first portion, laterally delimited by the STI insulation structure and selectively connectable to the conduction region, and wherein the power component comprises a further conduction contact, connected to the third portion of the semiconductor body.

10. Device according to claim 1, wherein the power component comprises a further conduction contact, connected to the first portion of the semiconductor body and crossing the STI insulation structure perpendicularly to the surface of the first portion of the semiconductor body.

11. Process for manufacturing an integrated device comprising:

in a semiconductor body, forming an STI insulation structure extending above a depressed first portion of the semiconductor body and laterally delimiting second portions of the semiconductor body projecting from the first portion;

forming low-voltage CMOS components in the second portions, in a first region of the semiconductor body; and

forming a power component in a second region of the semiconductor body;

wherein forming the power component comprises;

forming at least one conduction region, in the first portion of the semiconductor body; and

forming a conduction contact, connected to the conduction region and crossing the STI insulation structure perpendicularly to the surface of the first portion of the semiconductor body.

12. Process according to claim 11, comprising forming an aperture through the STI insulation structure.

13. Process according to claim 12 wherein forming at least one conduction region comprises implanting a doping species in the first portion of the semiconductor body through the aperture.

14. Process according to claim 11, wherein the conduction region is a source region.

15. Process according to claim 11, comprising forming a body region in the first portion of the semiconductor body and wherein the conduction region is formed in the body region.

16. Process according to claim 15, comprising forming a gate region in part above the STI insulation structure and in part in the aperture, above a junction region of the semiconductor body adjacent to the body region, above a channel region, defined by a portion of the body region comprised between the junction region and the conduction region, and above part of the conduction region.

17. A semiconductor structure, comprising:

a semiconductor region;

a first source region disposed at a first level of the semiconductor region; and

a second source region disposed at a second level of the semiconductor region.

18. The semiconductor structure of claim 17 wherein the semiconductor region comprises a substrate.

19. The semiconductor structure of claim 17 wherein the semiconductor region comprises an epitaxial region.

20. The semiconductor structure of claim 17 wherein:

the semiconductor region comprises a first surface at the first level and a second surface at the second level;

the first source is disposed contiguous with the first surface; and

the second source is disposed contiguous with the second surface.

21. The semiconductor structure of claim 17, further comprising:

a lower-power transistor that includes the first source region; and

a higher-power transistor that includes the second source region.

22. The semiconductor structure of claim 17, further comprising:

a first isolation region disposed in the semiconductor region at substantially the first level and adjacent to the first source region; and

a second isolation region disposed in the semiconductor region at substantially the first level and adjacent to the second source region.

23. The semiconductor structure of claim 17, further comprising:

a first isolation region disposed in the semiconductor region at substantially the first level and having a sidewall with a first slope adjacent to the first source region; and

a second isolation region disposed in the semiconductor region at the substantially the first level and having a sidewall with a second slope adjacent to the second source region.

24. The semiconductor structure of claim 17, further comprising:

a first isolation region disposed in the semiconductor region substantially at the first level and having a sidewall with a slope having a first magnitude adjacent to the first source region; and

a second isolation region disposed in the semiconductor region substantially at the first level and having a sidewall with a slope having a second magnitude adjacent to the second source region.

25. The semiconductor structure of claim 17, further comprising:

a lower-power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region at substantially the first level; and

a higher-power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region at substantially the first level.

26. The semiconductor structure of claim 17, further comprising:

a lower-power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first level; and

a higher-power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the first level.

27. The semiconductor structure of claim 17, further comprising:

a lower-power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region at substantially the first level; and

a higher-power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region at substantially the second level.

28. The semiconductor structure of claim 17, further comprising:

a lower-power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first level; and

a higher-power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the second level.

29. The semiconductor structure of claim 17, further comprising:

a lower-power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first level;

a first isolation region disposed in the semiconductor region substantially at the first level and having a sidewall with a slope having a magnitude adjacent to the first drain region;

a higher-power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the first level; and

a second isolation region disposed in the semiconductor region substantially at the first level and having a sidewall with a slope having substantially the magnitude adjacent to the second drain region.

30. The semiconductor structure of claim 17, further comprising:

a lower-power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first level;

a first isolation region disposed in the semiconductor region substantially at the first level and having a sidewall with a slope having a first magnitude adjacent to the first drain region;

a higher-power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the second level; and

a second isolation region disposed in the semiconductor region substantially at the first level and having a sidewall with a slope having a second magnitude adjacent to the second drain region.

31. The semiconductor structure of claim 17, further comprising:

a lower-power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first level;

a first isolation region disposed in the semiconductor region substantially at the first level and having a sidewall with a slope having a first magnitude adjacent to the first source and drain regions;

a higher-power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the first level; and

a second isolation region disposed in the semiconductor region substantially at the first level and having a first sidewall with a slope having a second magnitude adjacent to the second source region and having a second sidewall with a slope having substantially the first magnitude adjacent to the second drain region.

32. The semiconductor structure of claim 17, further comprising:

a lower-power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first level;

a first isolation region disposed in the semiconductor region substantially at the first level and having a sidewall with a slope having a first magnitude adjacent to the first source and drain regions;

a higher-power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the second level; and

a second isolation region disposed in the semiconductor region substantially at the first level and having a first sidewall with a slope having a second magnitude adjacent to the second source region and having a second sidewall with a slope having substantially the second magnitude adjacent to the second drain region.

33. An integrated circuit, comprising:

a die having a surface and a semiconductor layer disposed below the surface;

a first source region disposed in the semiconductor layer at a first distance from the surface; and

a second source region disposed in the semiconductor layer at a second distance from the surface.

34. The integrated circuit of claim 33, further comprising:

a lower-power transistor that includes the first source region; and

a higher-power transistor that includes the second source region.

35. The integrated circuit of claim 33, further comprising:

a first isolation region disposed in the semiconductor layer at substantially the first distance from the surface and adjacent to the first source region; and

a second isolation region disposed in the semiconductor layer at substantially the first distance from the surface and adjacent to the second source region.

36. The integrated circuit of claim 33, further comprising:

a first isolation region disposed in the semiconductor layer at substantially the first distance from the surface and having a sidewall with a first slope adjacent to the first source region; and

a second isolation region disposed in the semiconductor layer at substantially the first distance from the surface and having a sidewall with a second slope adjacent to the second source region.

37. The integrated circuit of claim 33, further comprising:

a first isolation region disposed in the semiconductor layer substantially at the first distance from the surface and having a sidewall with a slope having a first magnitude adjacent to the first source region; and

a second isolation region disposed in the semiconductor layer substantially at the first distance from the surface and having a sidewall with a slope having a second magnitude adjacent to the second source region.

38. The integrated circuit of claim 33, further comprising:

a lower-power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface; and

a higher-power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface.

39. The integrated circuit of claim 33, further comprising:

a lower-power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface; and

a higher-power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the second distance from the surface.

40. The integrated circuit of claim 33, further comprising:

a lower-power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface;

a first isolation region disposed in the semiconductor region substantially at the first distance from the surface level and having a sidewall with a slope having a first magnitude adjacent to the first drain region;

a higher-power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the second distance from the surface; and

a second isolation region disposed in the semiconductor region substantially at the first distance from the surface and having a sidewall with a slope having a second magnitude adjacent to the second drain region.

41. The integrated circuit of claim 33, further comprising:

a lower-power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface;

a first isolation region disposed in the semiconductor region substantially at the first distance from the surface and having a sidewall with a slope having a first magnitude adjacent to the first source and drain regions;

a higher-power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface; and

a second isolation region disposed in the semiconductor region substantially at the first distance from the surface and having a first sidewall with a slope having a second magnitude adjacent to the second source region and having a second sidewall with a slope having substantially the first magnitude adjacent to the second drain region.

42. The integrated circuit of claim 33, further comprising:

a lower-power transistor that includes the first source region and that includes a first drain region disposed in the semiconductor region and having at least a portion at substantially the first distance from the surface;

a first isolation region disposed in the semiconductor region substantially at the first distance from the surface and having a sidewall with a slope having a first magnitude adjacent to the first source and drain regions;

a higher-power transistor that includes the second source region and that includes a drain region disposed in the semiconductor region and having at least a portion at substantially the second distance from the surface; and

a second isolation region disposed in the semiconductor region substantially at the first distance from the surface and having a first sidewall with a slope having a second magnitude adjacent to the second source region and having a second sidewall with a slope having substantially the second magnitude adjacent to the second drain region.

43. A system, comprising:

a first integrated circuit, comprising;

a die having a surface and a semiconductor layer disposed below the surface;

a first source region disposed in the semiconductor layer at a first distance from the surface; and

a second source region disposed in the semiconductor layer at a second distance from the surface; and

a second integrated circuit coupled to the first integrated circuit.

44. The system of claim 43 wherein the first and second integrated circuits are disposed on a same die.

45. The system of claim 43 wherein the first and second integrated circuits are disposed on respective dies.

46. The system of claim 43 wherein at least one of the first and second integrated circuits comprises a controller.

47. A method, comprising:

forming a first source region of a first transistor at a first level of a semiconductor region; and

forming a second source region of a second transistor at a second level of the semiconductor region.

48. The method of claim 47 wherein:

forming the first source region at the first level comprises forming the first source region at a first surface of the semiconductor region; and

forming the second source region of the second level comprises forming the second source region at a second surface of the semiconductor region.

49. The method of claim 47, further comprising:

forming a first isolation region in the semiconductor region;

wherein forming the first source region comprises forming the first source region adjacent to the first isolation region;

forming a second isolation region in the semiconductor region;

forming in the second isolation region a first opening that exposes a first portion of the semiconductor region; and

wherein forming the second source region comprises forming the second source region in the exposed portion of the semiconductor region.

50. The method of claim 49, further comprising:

forming a first drain region of the first transistor in the semiconductor region adjacent to the first isolation region; and

forming a second drain region of the second transistor in the semiconductor region adjacent to the second isolation region.

51. The method of claim 49, further comprising:

forming a first drain region of the first transistor in the semiconductor region adjacent to the first isolation region;

forming in the second isolation region a second opening that exposes a second portion of the semiconductor region; and

forming a second drain region of the second transistor in the exposed second portion of the second isolation region.

52. The method of claim 47, further comprising:

forming a first isolation region in the semiconductor region;

wherein forming the first source region comprises forming the first source region adjacent to the first isolation region;

forming a second isolation region in the semiconductor region;

isotropically etching the second isolation region to form an opening that exposes a portion of the semiconductor region; and

wherein forming the second source region comprises forming the second source region in the exposed portion of the semiconductor region.