DYNAMICALLY RECONFIGURABLE ANALOG ROUTING CIRCUITS AND METHODS FOR SYSTEM ON A CHIP

• US 20110026519A1
• Filed: 05/07/2010
• Published: 02/03/2011
• Est. Priority Date: 05/09/2009
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Hastings, Mark, Shutt, James, Thiagarajan, Eashwar, Richmond, Melany Ann, Kutz, Harold, Snyder, Warren, Byrkett, Bruce E., Sullam, Bert, Williams, Timothy, Kohagen, Nathan
• Granted Patent: US 9,612,987 B2
• Time in Patent Office: Days
• US Class Current: 370/360
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 2213/0038 System on Chip

Abstract

An integrated circuit device may include a reconfigurable analog signal switching fabric comprising a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to changeable analog routing data, and a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and at least one processor circuit that executes predetermined operations in response to instruction data.

Claims

1. An integrated circuit device, comprising:

a dynamically or statically reconfigurable analog signal switching fabric comprising

a plurality of global buses that are selectively connected to external pins by pin connection circuits in response to analog routing data, and

a plurality of local buses that are selectively connected to analog blocks and/or global buses by routing connection circuits in response to the analog routing data; and

at least one processor circuit that executes predetermined operations in response to instruction data.

2. The integrated circuit device of claim 1, wherein:

the pin connection circuits comprise switch circuits that selectively connect one external pin to any of a plurality of global buses in response to the analog routing data.

3. The integrated circuit device of claim 1, wherein:

the pin connection circuits comprise multiplexer circuits that selectively connect one external pin to any one of a plurality of global buses in response to the analog routing data.

4. The integrated circuit of claim 1, wherein:

the routing connection circuits comprise switch circuits that selectively connect at least one analog block to any of the local buses and/or global buses in response to the analog routing data.

5. The integrated circuit of claim 1, wherein:

the routing connection circuits include

first routing connection circuits that provide connections having a first impedance, and

second routing connection circuits that provide connections having a second impedance less than the first impedance.

6. The integrated circuit of claim 1, wherein:

the local buses and global buses are shielded to reduce signal coupling therebetween.

7. The integrated circuit device of claim 1, wherein:

the reconfigurable analog signal switching fabric further includes

at least one multiplexer (MUX) bus selectively connected to any of the pins by the pin connection circuits and to at least one global and/or local bus by the routing connection circuits.

8. The integrated circuit device of claim 1, further including:

a programmable logic section comprising a plurality of digital programmable blocks; and

a digital system interconnect that provides the analog routing data from at least the programmable logic section or the at least one processor circuit.

9. The integrated circuit of claim 8, further including:

a direct access circuit coupled to transfer data between the integrated circuit and a source external to the integrated circuit; and

the digital system interconnect also provides the analog routing data from the direct access circuit.

10. An integrated circuit, comprising:

at least one processor circuit;

a plurality of analog circuit blocks; and

a dynamically or statically reconfigurable analog routing fabric that selectively interconnects the analog circuit blocks and input/output (I/O) pins in response to analog routing data from at least one routing data source in addition to the at least one processor circuit.

11. The integrated circuit device of claim 10, wherein:

the at least one other routing data source is selected from;

a programmable digital logic section formed in the integrated circuit, and a direct access circuit that transfers data between the integrated circuit and a source external to the integrated circuit.

12. The integrated circuit device of claim 10, wherein:

the reconfigurable analog routing fabric includes connection circuits selected from;

switch circuits that provide connections between single fabric points and any of multiple other fabric points, and multiplexer circuits that provide a single connection between a single fabric point and one of multiple other fabric points.

13. The integrated circuit device of claim 12, wherein:

at least one voltage generation circuit that generate at least one switch voltage outside a range of power supply voltages received by the integrated circuit, and provides the at least one switch voltage to at least one connection circuit.

14. The integrated circuit of claim 10, wherein:

the reconfigurable analog routing fabric includes

input/output (I/O) connection circuits corresponding to each of a plurality of I/O pins, each I/O connection circuit selectively connecting its I/O pin to at least one multiplexer (MUX) bus and/or at least one of a plurality of global buses;

wherein

the global buses are connectable to the analog circuit blocks through the analog routing fabric.

15. The integrated circuit of claim 10, wherein:

the reconfigurable analog routing fabric includes

routing connection circuits, each corresponding to an analog circuit block, that selectively connects its analog circuit block to any of a plurality of local buses;

wherein

the local buses are connectable to input/output (I/O) pins through the analog routing fabric.

16. The integrated circuit of claim 10, wherein:

the analog circuit blocks include two selected from;

an analog signal filter, a comparator, a capacitance sensing circuit, a switched capacitor circuit, an digital-to-analog converter, an analog-to-digital converter, and an operational amplifier.

17. A method, comprising:

in response to routing data, configuring a reconfigurable analog routing fabric on an integrated circuit to selectively enable connections between a plurality of input/output (I/O) pins and at least one of a plurality of global buses, and to selectively enable connections between at least one global bus and at least one of a plurality of analog circuit blocks of the integrated circuit;

wherein

the routing data is dynamically or statically provided from digital circuits of the integrated circuit.

18. The method of claim 17, wherein:

the configuring further includes

selectively enabling connections between the plurality of I/O pins and a same multiplexer bus, and

selectively enabling connections between the multiplexer bus and at least one of the analog circuit blocks.

19. The method of claim 17, wherein:

the routing data may be provided from a processor of the integrated circuit and either of;

programmable digital circuits of the integrated circuit, and a direct access circuit of the integrated circuit that transfers data between the integrated circuit and a location external to the integrated circuit.

20. The method of claim 17, wherein:

the configuring further includes

selectively enabling connections between a plurality of local buses and the analog circuit blocks to chain at least two analog circuit blocks together.