METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE

• US 20110031997A1
• Filed: 10/12/2009
• Published: 02/10/2011
• Est. Priority Date: 04/14/2009
• Status: Abandoned Application

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: NuPGA Corporation
• Inventors: Arghavani, Reza, Wurman, Zeev, Beinglass, Israel, Cronquist, Brian, Or-Bach, Zvi
• Application Number:
  US12/577,532
• Publication Number:
  US 20110031997A1
• Time in Patent Office: Days
• US Class Current: 326/37
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A method is presented that may be used to provide a Configurable Logic device, which may be Field Programmable with volume flexibility. A method of fabricating an integrated circuit may include the steps of: providing a semiconductor substrate and forming a borderless logic array, and it may also include the step of forming a plurality of antifuse configurable interconnect circuits and/or a plurality of transistors to configure at least one antifuse. The programming transistors may be fabricated over the at least one antifuse.

Claims

1. A programmable logic device comprising:

a first single crystal silicon layer; and

a second thin single crystal silicon layer of less than 10 micron thickness overlying said first single crystal silicon layer,

wherein said second thin single crystal silicon layer comprises a plurality of transistors forming programmable logic.

2. A programmable logic device according to claim 1 wherein said programmable logic comprises antifuses and said first single crystal silicon layer comprises transistors for programming at least one of said antifuses.

3. A semiconductor device comprising:

a first single crystal silicon layer; and

a second thin single crystal silicon layer of less than 10 micron thickness overlying said first single crystal silicon layer,

wherein said second thin single crystal silicon layer comprises a plurality of first transistors forming device circuitry, and

said first single crystal silicon layer comprises a plurality of second transistors forming at least a portion of input/output circuitry for the device,

wherein the second transistors are larger than the first transistors.

4. A programmable logic device comprising:

a first crystallized silicon layer; and

a second thin single crystal silicon layer of less than 10 micron thickness overlying said first single crystal silicon layer,

wherein said first single crystal silicon layer comprises a plurality of transistors forming programmable logic.

5. A programmable logic device according to claim 4 wherein said programmable logic comprises antifuses and said second thin single crystal silicon layer comprises transistors for programming at least one of said antifuses.

6. A semiconductor device comprising:

a first single crystal silicon layer having a plurality of first transistors and multiple metal layers on top of said first transistors forming device circuitry; and

a second thin single crystal silicon layer of less than 2 micron thickness overlying said first single crystal silicon layer,

wherein said second thin single crystal silicon layer comprises a plurality of second transistors electrically connected to said first transistors,

wherein said second transistors are defined by etching said second thin single crystal silicon layer after overlaying said second thin single crystal silicon layer on said first single crystal silicon layer, and

wherein said second transistors each have a source and a drain in one sub-layer of said second thin crystal silicon layer.

7. A semiconductor device comprising:

a first single crystal silicon layer comprising a plurality of first transistors and multiple metal layers on top of said first transistors forming device circuitry, said multiple metal layers having an upper first top metal layer, wherein at least one of said multiple metal layers has a temperature limit of approximately 400°

C.; and

a second thin single crystal silicon layer of less than 2 micron thickness overlying said multiple metal layers,

wherein said second thin single crystal silicon layer comprising a plurality of second transistors is offset less than 100 nm to said first top metal layer, and

wherein said second transistors each have a source and a drain in one sub-layer of said second thin crystal silicon layer.