Method for Fabrication of a Semiconductor Device and Structure
First Claim
Patent Images
1. An Integrated Circuit device comprising:
- a plurality of antifuse-configurable interconnect circuits; and
a plurality of transistors arranged to configure at least one antifuse of said antifuse-configurable interconnect circuits, wherein said transistors are above said antifuse-configurable interconnect circuits.
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Abstract
A novel method is presented that may be used to provide a Configurable Logic device, which may be Field Programmable with volume flexibility. A method of fabricating an integrated circuit may include the steps of: providing a semiconductor substrate and forming a borderless logic array, and it may also include the step of forming a plurality of antifuse configurable interconnect circuits and/or a plurality of transistors to configure at least one antifuse. The programming transistors may be fabricated over the antifuse.
108 Citations
25 Claims
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1. An Integrated Circuit device comprising:
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a plurality of antifuse-configurable interconnect circuits; and a plurality of transistors arranged to configure at least one antifuse of said antifuse-configurable interconnect circuits, wherein said transistors are above said antifuse-configurable interconnect circuits. - View Dependent Claims (2, 3, 4, 9, 10)
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5. An Integrated Circuit device comprising:
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a first antifuse layer; at least two metal layers over the first antifuse layer; and a second antifuse layer over said at least two metal layers. - View Dependent Claims (6, 7, 8)
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11. An integrated circuit system comprising:
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a configurable logic die; and an I/O die, wherein said configurable logic die is connected to said I/O die by the use of at least one through-silicon-via; and wherein said configurable logic die comprises one or more antifuses. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. An Integrated Circuit device comprising:
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a semiconductor substrate; a multiplicity of metal layers; a plurality of antifuse-configurable interconnect circuits; and a plurality of transistors arranged to configure at least one antifuse of the antifuse-configurable interconnect circuits, wherein said antifuse-configurable interconnect layer is fabricated within said multiplicity of metal layers so as to allow connection between at least two of said metal layers, and wherein said transistors are fabricated above said antifuse. - View Dependent Claims (19, 20, 25)
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21. An integrated circuit system comprising:
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a configurable logic die, wherein said configurable logic die comprises a semiconductor substrate; an I/O die, wherein said configurable logic die is connected to said I/O die by the use of at least one through-silicon-via; a multiplicity of metal layers; a plurality of antifuse-configurable interconnect circuits; and a plurality of transistors arranged to configure at least one antifuse of said antifuse-configurable interconnect circuits, wherein said at least one antifuse is fabricated within said multiplicity of metal layers so as to allow connection between at least two of said metal layers. - View Dependent Claims (22, 23, 24)
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Specification