Semiconductor device and structure

• US 8,384,426 B2
• Filed: 04/14/2009
• Issued: 02/26/2013
• Est. Priority Date: 04/14/2009
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi
• Primary Examiner(s): Ismail, Shawki S
• Assistant Examiner(s): LO, CHRISTOPHER KWOK YEUNG
• Application Number:
  US12/423,214
• Publication Number:
  US 20110037497A1
• Time in Patent Office: 1,414 Days
• Field of Search: 326 37- 47, 257/499, 257/773, 257/774, 257/797, 438/197, 438/401, 438/458
• US Class Current: 326/39
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters

Abstract

A novel Integrated Circuit device including a plurality of antifuse-configurable interconnect circuits, each circuit including: at least two interconnects, and at least one antifuse, wherein the antifuse is adapted to directly connect at least two interconnects. The Integrated Circuit device also includes a plurality of transistors adapted to configure at least one antifuse of the antifuse-configurable interconnect circuits, wherein the transistors are above the antifuse-configurable interconnect circuits.

Claims

1. An Integrated Circuit device comprising:

a plurality of antifuse-configurable interconnect circuits, each comprising;

at least two interconnects, and at least one antifuse, wherein said antifuse is adapted to directly connect at least two interconnects; and

a plurality of transistors, adapted arranged to configure at least one antifuse of said antifuse-configurable interconnect circuits, wherein said transistors are above said antifuse-configurable interconnect circuits, and wherein said antifuse is on a different layer than said transistors.

2. The Integrated Circuit device according to claim 1, wherein said transistors are fabricated after said antifuse-configurable interconnect circuits.

3. The Integrated Circuit device according to claim 1, further comprising:

a plurality of second antifuse-configurable logic cells; and

a plurality of second transistors arranged to configure at least one antifuse of said second antifuse-configurable logic cells,

wherein said second transistors are fabricated before said second antifuse-configurable logic cells.

4. The Integrated Circuit device according to claim 2, further comprising:

one or more second antifuse-configurable logic cells; and

one or more second transistors to configure one or more antifuses of said second antifuse-configurable logic cells,

wherein said second transistors are underneath said second antifuse-configurable logic cells.

5. The Integrated Circuit device according to claim 1, further comprising a non-volatile memory comprising at least one of said antifuse-configurable interconnect circuits.

6. The Integrated Circuit device according to claim 5, wherein at least one of the antifuse-configurable interconnect circuits is configurable as part of a PLA function.

11. The Integrated Circuit device of claim 1, further comprising a plurality of metal layers.

7. An Integrated Circuit device comprising:

a semiconductor substrate;

a multiplicity of metal layers;

a plurality of antifuse-configurable interconnect circuits; and

a plurality of transistors arranged to configure at least one antifuse of the antifuse-configurable interconnect circuits, wherein said antifuse-configurable interconnect circuits are fabricated within said multiplicity of metal layers so as to allow direct connection between at least two of said metal layers, and wherein said transistors are fabricated above said antifuse, and wherein said antifuse is on a different layer than said transistors.

8. The Integrated Circuit device according to claim 7, wherein said transistors are fabricated after said antifuse-configurable interconnect layer.

9. The Integrated Circuit device according to claim 7, further comprising:

one or more antifuse-configurable logic cells; and

a plurality of second transistors arranged to configure at least one antifuse of said one or more antifuse-configurable logic cells, wherein said second transistors are underneath said one or more antifuse-configurable logic cells.

10. The Integrated Circuit device according to claim 7, wherein said transistors are connected to at least one antifuse of the antifuse-configurable interconnect circuits by using at least one through-silicon-via.