DISPLAY SUBSTRATE, METHOD OF MANUFACTURING THE DISPLAY SUBSTRATE, AND DISPLAY DEVICE HAVING THE DISPLAY SUBSTRATE

• US 20110079782A1
• Filed: 07/20/2010
• Published: 04/07/2011
• Est. Priority Date: 10/06/2009
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Kyeong-Hyeon, KIM, Hyun-Wuk, Shin, Sung-Tae
• Granted Patent: US 8,502,243 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: G02F 1/133516 Methods for their manufacture, e.g. printing, electro-deposition or photolithography
• CPC Class Codes: G02F 1/133528 Polarisers
• CPC Class Codes: G02F 1/133541 Circular polarisers
• CPC Class Codes: G02F 2203/10 plasmon
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate

Abstract

A display substrate includes a base substrate, a first dielectric layer, a first lattice pattern, a second lattice pattern, and a second dielectric layer. The first lattice pattern is disposed on the first dielectric layer at a first color pixel region. The first lattice pattern includes a plurality of first nano metal wires. The second lattice pattern is disposed on the first dielectric layer at a second color pixel region. The second lattice pattern includes a plurality of second nano metal wires. The second nano metal wires have different dimensions from the first nano metal wires. The second dielectric layer covers the first nano metal wires and the second nano metal wires.

Claims

1. A display substrate comprising:

a base substrate;

a first dielectric layer disposed on the base substrate;

a first lattice pattern disposed on the first dielectric layer at a first color pixel region, the first lattice pattern including a plurality of first nano metal wires;

a second lattice pattern disposed on the first dielectric layer at a second color pixel region, the second lattice pattern including a plurality of second nano metal wires, the second nano metal wires having different dimensions from the first nano metal wires; and

a second dielectric layer disposed on the first lattice pattern and the second lattice pattern, the second dielectric layer covering the first nano metal wires and the second nano metal wires.

2. The display substrate of claim 1, wherein each of the first nano metal wires and the second nano metal wires comprises:

a main wire containing a first metal; and

a sub wire disposed adjacent to the main wire, the sub wire containing a second metal different from the first metaland having different dimensions from the main wire.

3. The display substrate of claim 1, wherein the first dielectric layer and the second dielectric layer contain the same dielectric material.

4. The display substrate of claim 1, further comprising:

a thin-film transistor including a gate electrode connected to a gate line, a source electrode connected to a data line, and a drain electrode separated from the source electrode; and

a pixel electrode disposed on the second dielectric layer and electrically connected to the thin-film transistor.

5. The display substrate of claim 1, wherein at least one of a width, a thickness, and an arranging period of the second nano metal wires is different from that of the first nano metal wires.

6. The display substrate of claim 1, further comprising a thin-film transistor including a gate electrode connected to a gate line, a source electrode connected to a data line, and a drain electrode separated from the source electrode,

wherein the first dielectric layer is formed on the base substrate on which the data line, the source electrode and the drain electrode are formed, and

wherein a first pixel voltage and a common voltage are applied to adjacent first nano metal wires, and a second pixel voltage and the common voltage are applied to adjacent second nano metal wires.

7. The display substrate of claim 1, further comprising:

a light-blocking layer disposed at a boundary between the first pixel region and the second pixel region; and

a common electrode disposed on the light-blocking layer,

wherein the first dielectric layer is formed on the light-blocking layer to cover the light-blocking layer, and the common electrode is disposed on the second dielectric layer.

8. A method of manufacturing a display substrate, the method comprising:

forming a first dielectric layer on a base substrate;

forming a first lattice pattern and a second lattice pattern on the first dielectric layer, the first lattice pattern being disposed at a first color pixel region on the base substrate and including a plurality of first nano metal wires, the second lattice pattern being disposed at a second color pixel region on the base substrate and including a plurality of second nano metal wires, the second nano metal wires having different dimensions from the first nano metal wires; and

forming a second dielectric layer covering the first nano metal wires and the second nano metal wires.

9. The method of claim 8, wherein forming the first lattice pattern and the second lattice pattern comprises:

forming a first main wire of one of the first nano metal wires and a second main wire of one of the second nano metal wires with a first metal; and

forming a first sub wire and a second sub wire with a second metal, the first sub wire making contact with the first main wire, the second sub wire making contact with the second main wire.

10. The method of claim 8, further comprising:

forming a gate metal pattern on the second dielectric layer, the gate metal pattern including a gate line and a gate electrode;

forming a data metal pattern insulated from the gate metal pattern, the data metal pattern including a data line, a source electrode connected to the data line, and a drain electrode separated from the source electrode; and

forming a pixel electrode electrically connected to the drain electrode.

11. The method of claim 8, further comprising:

forming a gate metal pattern on the base substrate, the gate metal pattern including a gate line and a gate electrode; and

forming a data metal pattern insulated from the gate metal pattern, the data metal pattern including a data line, a source electrode connected to the data line, and a drain electrode separated from the source electrode,

wherein the first dielectric layer is formed to cover the data metal pattern.

12. The method of claim 8, further comprising:

forming a light-blocking layer at a boundary between the first pixel region and the second pixel region on the base substrate prior to forming the first dielectric layer; and

forming a common electrode on the second dielectric layer.

13. A display device comprising:

a first display substrate having;

a first base substrate defining a first color pixel region and a second color pixel region;

a first dielectric layer disposed on the first base substrate;

a first lattice pattern disposed on the first dielectric layer at the first color pixel region, the first lattice pattern including a plurality of first nano metal wires;

a second lattice pattern disposed on the first dielectric layer at the second color pixel region, the second lattice pattern including a plurality of second nano metal wires, the second nano metal wires having different dimensions from the first nano metal wires; and

a second dielectric layer disposed on the first lattice pattern and the second lattice pattern, the second dielectric layer covering the first nano metal wires and the second nano metal wires; and

a second display substrate comprising;

a second base substrate facing the first base substrate; and

a common electrode disposed on the second base substrate.

14. The display device of claim 13, wherein each of the first nano metal wires and the second nano metal wires includes:

a main wire comprising a first metal; and

a sub wire disposed adjacent to the main wire, the sub wire containing a second metal different from the first metal, the sub wire having different dimensions from the main wire.

15. The display device of claim 13, wherein at least one of a width, a thickness, and an arranging period of the second nano metal wires is different from that of the first nano metal wires.

16. A display device comprising:

a first display substrate having a pixel electrode disposed on a first base substrate; and

a second display substrate facing the first display substrate, the second display substrate comprising;

a second base substrate defining a first color pixel region and a second color pixel region adjacent to the first color pixel region;

a first dielectric layer disposed on the second base substrate;

a first lattice pattern disposed on the first dielectric layer at the first color pixel region, the first lattice pattern including a plurality of first nano metal wires;

a second lattice pattern disposed on the first dielectric layer at the second color pixel region, the second lattice pattern including a plurality of second nano metal wires, the second nano metal wire having different dimensions from that of the first nano metal wire;

a second dielectric layer disposed on the first lattice pattern and the second lattice pattern, the second dielectric layer covering the first nano metal wires and the second nano metal wires; and

a common electrode disposed on the second dielectric layer.

17. The display device of claim 16, wherein each of the first nano metal wire and the second nano metal wire comprises:

a main wire containing a first metal; and

a sub wire disposed adjacent to the main wire, the sub wire containing a second metal different from the first metal, the sub wire having different dimensions from the main wire.

18. The display device of claim 16, wherein at least one of a width, a thickness, and an arranging period of the second nano metal wire is different from that of the first nano metal wire.

19. A display device comprising:

a first display substrate comprising;

a thin-film transistor formed on a first base substrate defining a first color pixel region and a second color pixel region;

a first dielectric layer disposed on the first base substrate, the first dielectric layer covering the thin-film transistor;

a first lattice pattern disposed on the first dielectric layer at the first color pixel region, the first lattice pattern including a plurality of first nano metal wires;

a second lattice pattern disposed on the first dielectric layer at the second color pixel region, the second lattice pattern including a plurality of second nano metal wires, the second nano metal wire having different dimensions from that of the first nano metal wire; and

a second dielectric layer disposed on the first lattice pattern and the second lattice pattern, the second dielectric layer covering the first nano metal wires and the second nano metal wires; and

a second display substrate including a second base substrate facing the first base substrate.

20. The display device of claim 19, wherein a first pixel voltage and a common voltage are applied to adjacent first nano metal wires, and a second pixel voltage and the common voltage are applied to adjacent second nano metal wires.