Display substrate, method of manufacturing the display substrate, and display device having the display substrate

• US 8,502,243 B2
• Filed: 07/20/2010
• Issued: 08/06/2013
• Est. Priority Date: 10/06/2009
• Status: Expired due to Fees

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Kyeong-Hyeon, Kim, Hyun-Wuk, Shin, Sung-Tae
• Primary Examiner(s): REAMES, MATTHEW L
• Application Number:
  US12/840,202
• Publication Number:
  US 20110079782A1
• Time in Patent Office: 1,113 Days
• Field of Search: 257 88- 89, 257 88- 89, 257/E33.067, 257/E33.068
• US Class Current: 257/89
• CPC Class Codes: G02F 1/133516 Methods for their manufacture, e.g. printing, electro-deposition or photolithography
• CPC Class Codes: G02F 1/133528 Polarisers
• CPC Class Codes: G02F 1/133541 Circular polarisers
• CPC Class Codes: G02F 2203/10 plasmon
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate

Abstract

A display substrate includes a base substrate, a first dielectric layer, a first lattice pattern, a second lattice pattern, and a second dielectric layer. The first lattice pattern is disposed on the first dielectric layer at a first color pixel region. The first lattice pattern includes a plurality of first nano metal wires. The second lattice pattern is disposed on the first dielectric layer at a second color pixel region. The second lattice pattern includes a plurality of second nano metal wires. The second nano metal wires have different dimensions from the first nano metal wires. The second dielectric layer covers the first nano metal wires and the second nano metal wires.

Claims

1. A display substrate comprising:

a base substrate;

a first dielectric layer disposed on the base substrate;

a first lattice pattern disposed on the first dielectric layer at a first color pixel region, the first lattice pattern including a plurality of first nano metal wires having a first main wire and a first sub wire disposed on a side wall of the first main wire;

a second lattice pattern disposed on the first dielectric layer at a second color pixel region, the second lattice pattern including a plurality of second nano metal wires having a second main wire and a second sub wire disposed on a side wall of the second main wire, the second nano metal wires having different dimensions from the first nano metal wires; and

a second dielectric layer disposed on the first lattice pattern and the second lattice pattern, the second dielectric layer covering the first nano metal wires and the second nano metal wires,

wherein a thickness of the first sub wire is different from that of the second sub wire.

2. The display substrate of claim 1, further comprising pixel electrodes formed on the first lattice pattern and the second pixel electrodes.

3. The display substrate of claim 2, wherein the first dielectric layer and the second dielectric layer contain a same dielectric material.

4. The display substrate of claim 3, wherein at least one of a width, a thickness, and an arranging period of the second nano metal wires is different from that of the first nano metal wires.

5. The display substrate of claim 2, wherein at least one of a width, a thickness, and an arranging period of the second nano metal wires is different from that of the first nano metal wires.

6. The display substrate of claim 1, further comprising common electrodes formed on the first lattice pattern and the second pixel electrodes.

7. The display substrate of claim 6, wherein the first dielectric layer and the second dielectric layer contain a same dielectric material.

8. The display substrate of claim 7, wherein at least one of a width, a thickness, and an arranging period of the second nano metal wires is different from that of the first nano metal wires.

9. The display substrate of claim 6, wherein at least one of a width, a thickness, and an arranging period of the second nano metal wires is different from that of the first nano metal wires.

10. A color display device comprising:

a first display substrate comprising;

a thin-film transistor formed on a first base substrate defining a first color pixel region and a second color pixel region;

a first dielectric layer disposed on the first base substrate, the first dielectric layer covering the thin-film transistor;

a first lattice pattern disposed on the first dielectric layer at the first color pixel region, the first lattice pattern including a plurality of first nano metal wires having a first main wire and a first sub wire disposed on a side wall of the first main wire;

a second lattice pattern disposed on the first dielectric layer at the second color pixel region, the second lattice pattern including a plurality of second nano metal wires having a second main wire and a second sub wire disposed on a side wall of the second main wire, the second nano metal wire having different dimensions from that of the first nano metal wire; and

a second dielectric layer disposed on the first lattice pattern and the second lattice pattern, the second dielectric layer covering the first nano metal wires and the second nano metal wires;

a second display substrate including a second base substrate facing the first base substrate; and

a liquid crystal layer formed between the first display substrate and the second display substrate,

wherein a thickness of the first sub wire is different from that of the second sub wire.

11. The display device of claim 10, wherein the first and the second main wires include a first metal, and the first and the second sub wires include a second metal different from the first metal.