PROCESSOR PERFORMANCE ADJUSTMENT SYSTEM AND METHOD

• US 20110126056A1
• Filed: 02/01/2011
• Published: 05/26/2011
• Est. Priority Date: 11/14/2002
• Status: Abandoned Application

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Kransusch, Kevin, Lam, John, Kelleher, Brian M., Mimberg, Ludger, Velmurugan, Senthil S.
• Application Number:
  US13/019,249
• Publication Number:
  US 20110126056A1
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention performance enhancement and reliability maintenance system and method pushes a processor to its maximized performance capabilities when performing processing intensive tasks (e.g., 3D graphics, etc). For example, a clock speed and voltage are increased until an unacceptable error rate begins to appear in the processing results and then the clock speed and voltage are backed off to the last setting at which excessive errors did not occur, enabling a processor at its full performance potential. The present invention also includes the ability to throttle back settings which facilitates the maintenance of desired reliability standards. The present invention is readily expandable to provide adjustment for a variety of characteristics in response to task performance requirements. For example, a variable speed fan that is software controlled can be adjusted to alter the temperature of the processor in addition to clock frequency and voltage.

Claims

1. A processor adjustment system comprising:

a processing unit for performing processing tasks;

a voltage source unit for generating a power signal for said processing unit;

a performance testing component for testing the performance of said processing unit to determine a high voltage level or a low voltage level at which said processing unit begins to fail;

a voltage control component for controlling the voltage level of said power signal does not go above said high voltage level or below said low voltage level, wherein said power signal voltage is increased for high performance tasks and reduced for low performance tasks of said processing unit;

a memory for storing test suite instructions for execution by said performance testing component.

2. The processor adjustment system of claim 1 further comprising:

a clock signal generating unit for generating a clock signal for said processing unit; and

a clock control component for controlling the frequency of said clock signal, wherein said clock signal does not go above a high frequency level or below a low frequency level determined by said performance testing component, wherein said clock signal frequency is increased for high performance tasks and reduced for low performance tasks of said processing unit.

3. The processor adjustment system of claim 1 wherein said processing unit is a graphics processor.

4. The processor adjustment system of claim 1 wherein said testing is performed at each power up of said system.

5. The processor adjustment system of claim 1 wherein the performance nature of said task is user defined.

6. The processor adjustment system of claim 1 wherein the performance nature of said task is defined by an application program executing said task.

7. The processor adjustment system of claim 1 wherein said testing is performed periodically.

8. A processor adjustment system comprising:

a processing unit for performing processing tasks;

a clock signal generating unit for generating a clock signal for said processing unit;

a performance testing component for periodically testing the performance of said processing unit to determine a high clock frequency or a low clock frequency at which said processing unit begins to fail; and

a clock control component for controlling the frequency of said clock signal above said high clock frequency or below said low clock frequency determined by said performance testing component, wherein said clock signal frequency is increased for high performance tasks and reduced for low performance tasks of said processing unit; and

a memory for storing test suit e instructions for execution by said performance testing component.

9. The processor adjustment system of claim 8 wherein said performance testing component also determines a minimum clock frequency at which said processing unit begins to fail.

10. The processor adjustment system of claim 8 wherein said performance testing component is controlled by software running on a CPU, said CPU being different from said processing unit.

11. The processor adjustment system of claim 8 further comprising a voltage control component for controlling the voltage level of a power signal for said processing unit, wherein said power signal voltage is set to a higher voltage for said high performance tasks than for said low performance tasks.

12. The processor adjustment system of claim 8 wherein said processor is a graphics processor.

13. The processor adjustment system of claim 12 wherein said high performance tasks comprise rendering interactive three-dimensional graphics images.

14. The processor adjustment system of claim 13 wherein said low performance tasks do not comprise rendering interactive three-dimensional graphics images.

15. A processor adjustment system of claim 8 wherein said test suite instructions are based upon binning of said processor unit and said memory on an individual and combined board basis.

16. A processor adjustment system of claim 8 wherein said test suite instructions are changed in response to results of a self test operation.

17. A processor performance enhancement and reliability balancing method comprising:

storing test suite instructions in a memory for execution by a performance testing component;

testing processor performance, wherein said testing comprises determining a high clock frequency or a low clock frequency at which said processor begins to fail;

making an adjustment above said low clock frequency or below said high clock frequency to reduce a failure rate;

determining if said processor is engaged in a high performance task, wherein said high performance tasks comprise rendering three-dimensional graphics images;

adjusting operating condition settings for a high performance task including increasing the speed of a fan during said high performance task;

determining if said processor is engaged in a low performance task; and

adjusting operating condition setting for a low performance task, including decreasing the speed of a fan during said low performance task.

18. The processor performance enhancement and reliability balancing method of claim 17 wherein said testing provides an indication of errors.

19. The processor performance enhancement and reliability balancing method of claim 18 wherein said indication of an error occurring does not trigger an operating condition adjustment unless a predetermined unacceptable level of errors occur.

20. The processor performance enhancement and reliability balancing method of claim 19 wherein crossing a threshold triggers tests that determine said adjustment to said operating condition.