THIN FILM TRANSISTOR AND METHOD OF FORMING THE SAME

• US 20110147735A1
• Filed: 08/30/2010
• Published: 06/23/2011
• Est. Priority Date: 12/17/2009
• Status: Abandoned Application

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Cheong, Woo-Seok
• Application Number:
  US12/871,448
• Publication Number:
  US 20110147735A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Provided are a thin film transistor and a method of forming the same. The thin film transistor includes: a substrate; a source electrode and a drain electrode on the substrate; an oxide active layer between the source electrode and the drain electrode; a gate electrode on one side of the oxide active layer; a gate dielectric layer between the gate electrode and the oxide active layer; and a buffer layer between the gate dielectric layer and the oxide active layer.

Claims

1. A thin film transistor comprising:

a substrate;

source/drain electrodes on the substrate;

an oxide active layer between the source/drain electrodes;

a gate electrode on one side of the oxide active layer;

a gate dielectric layer between the gate electrode and the oxide active layer; and

a buffer layer between the gate dielectric layer and the oxide active layer.

2. The thin film transistor of claim 1, wherein the buffer layer comprises a silicon oxide, a silicon nitride, or a combination thereof.

3. The thin film transistor of claim 2, wherein the buffer layer has a thickness of about 1 nm to about 20 nm.

4. The thin film transistor of claim 1, wherein:

the source/drain electrodes are disposed adjacent to the substrate;

the oxide active layer is disposed on the substrate between the source/drain electrodes;

the gate dielectric layer is disposed on the oxide active layer; and

the buffer layer is disposed between the oxide active layer and the gate dielectric layer.

5. The thin film transistor of claim 1, wherein:

the gate electrode is disposed adjacent to the substrate;

the gate dielectric layer and the buffer layer are sequentially stacked on the substrate including the gate electrode;

the oxide active layer is disposed on the buffer layer on the gate electrode; and

the source/drain electrodes are disposed on the buffer layer beside the active layer.

6. The thin film transistor of claim 1, wherein the oxide active layer comprises at least one oxide selected from Group 3A, 4A, and 5A, and Group 2B, 3B, and 4B metals.

7. The thin film transistor of claim 6, wherein the oxide active layer comprises at least one of ZnO, In—

Zn—

O, Zn—

Sn—

O, In—

Ga—

ZnO, Zn—

In—

Sn—

O, In—

Ga—

O, and SnO₂.

8. The thin film transistor of claim 1, wherein the gate dielectric layer comprises alumina.

9. A method of forming a thin film transistor, the method comprising:

forming a source/drain electrode, a gate dielectric layer, a buffer layer contacting the gate dielectric layer, an oxide active layer, and a gate electrode, on a substrate; and

performing a thermal treatment process on the gate dielectric layer and the buffer layer, wherein;

the oxide active layer is formed on the substrate between the source/drain electrodes;

the gate dielectric layer is formed on side of the oxide active layer;

the buffer layer is formed on one side of the gate dielectric layer; and

the gate electrode is spaced apart from the oxide active layer by the gate dielectric layer.

10. The method of claim 9, wherein the forming of the source/drain electrodes, the gate dielectric layer, the buffer layer, the oxide active layer, and the gate electrode comprises:

forming the gate electrode on the substrate;

forming the gate dielectric layer and the buffer layer covering the gate electrode; and

forming the source/drain electrodes and the oxide active layer on the buffer layer at both sides of the gate electrode.

11. The method of claim 9, wherein the forming of the source/drain electrodes, the gate dielectric layer, the buffer layer, the oxide active layer, and the gate electrode comprises:

forming the source/drain electrodes and the oxide active layer on the substrate;

forming the buffer layer and the gate dielectric layer to cover the oxide active layer; and

forming the gate electrode on the gate dielectric layer.

12. The method of claim 9, wherein the thermal treatment is performed under a temperature of about 100°

C. to about 300°

C.

13. The method of claim 9, wherein the gate dielectric layer comprises alumina.

14. The method of claim 9, wherein the buffer layer comprises a silicon oxide, a silicon nitride, or a combination thereof, and is formed under a room temperature to a temperature of about 500°

C.

15. The method of claim 14, wherein the buffer layer is formed through a plasma enhanced chemical vapour deposition method.

16. The method of claim 9, wherein the oxide active layer comprises at least one oxide selected from Group 3A, 4A, and 5A and Group 2B, 3B, and 4B metals.

17. The method of claim 9, wherein the gate electrode and the source/drain electrodes comprise at least one selected from a metal and a metal oxide.