Biasing methods and devices for power amplifiers

• US 20110181364A1
• Filed: 01/25/2010
• Published: 07/28/2011
• Est. Priority Date: 01/25/2010
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Ahadian, Joseph F., Adamski, Jaroslaw E., Sharma, Vikas, Calanca, Neil
• Granted Patent: US 8,111,104 B2
• Time in Patent Office: Days
• US Class Current: 330/290
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/301 in MOSFET amplifiers H03F1/303, H03F1/305, H03F1/308 take precedence
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 3/2176 Class E amplifiers

Abstract

Biasing methods and devices for power amplifiers are described. The described methods and devices use the power amplifier output voltage to generate bias voltages. The bias voltages are obtained using rectifiers and voltage dividers. The described biasing methods and devices can be used with class-E power amplifiers.

Claims

1. A biasing method comprising the steps of:

providing an amplifier having an amplifier input and an amplifier output;

tapping the amplifier output to generate an AC voltage;

rectifying the AC voltage to generate a rectified voltage, and

dividing the rectified voltage to produce one or more bias voltages to bias the amplifier.

2. The biasing method of claim 1, wherein the AC voltage is generated by using an AC voltage divider comprising an in-series arrangement of one or more resistors and one or more capacitors.

3. The biasing method of claim 1, wherein the rectified voltage is generated using a voltage rectifier comprising a diode coupled in series with a capacitor.

4. The biasing method of claim 1, wherein the one or more bias voltages are generated by a DC voltage divider comprising two or more resistors coupled together in series.

5. The biasing method of claim 1, further comprising providing a bias source to generate one or more pre-bias voltages;

and wherein the bias source has a bias source DC output voltage.

6. The biasing method of claim 5, wherein the bias source DC output voltage is either fixed or variable.

7. A biasing method for class-E power amplifiers comprising the steps of:

providing a class-E power amplifier comprising a plurality of MOSFET devices adapted operate in an ON state or an OFF state, wherein the class-E power amplifier has an output that is coupled to a load network;

generating an amplifier output voltage at the amplifier output;

providing a biasing capacitance receiving the amplifier output voltage at one end and generating an AC voltage at another end;

generating a resonance condition through a combination of the biasing capacitance with the load network when the plurality of MOSFET devices are in the OFF state, and

rectifying the AC voltage to generate one or more bias voltages to the class-E power amplifier.

8. The biasing method of claim 7, wherein the load network comprises a parallel capacitance, a series capacitance and a series inductance.

9. The biasing method of claim 8, wherein the resonance condition is generated through parallel connection between the biasing capacitance and the parallel capacitance when the plurality of the MOSFET devices are in the OFF state.

10. The biasing method of claim 7, wherein in the AC voltage is obtained with an AC voltage divider comprising an in-series arrangement of one or more resistors and the biasing capacitor.

11. The biasing method of claim 7, wherein in the AC voltage is rectified with a voltage rectifier comprising a diode in series with a capacitor.

12. The biasing method of claim 7, wherein the one or more bias voltages are produced with a DC voltage divider comprising two or more resistors in series.

13. The biasing method of claim 7, further comprising providing a bias source to generate one or more pre-bias voltages;

the bias source having a bias source DC output voltage.

14. The biasing method of claim 13, wherein the bias source DC output voltage is fixed or controllable.

15. A bias circuit connectable, during operation, to a power amplifier comprising a plurality of MOSFET devices to produce a power amplifier AC output voltage at a power amplifier output, the bias circuit comprising:

a rectifier, the rectifier having a rectifier DC voltage output and rectifying an AC voltage originated from the power amplifier AC output voltage to a DC voltage at the rectifier DC voltage output, the DC voltage being input, during operation, to one or more gate terminals of the MOSFET devices of the power amplifier.

16. The bias circuit of claim 15, further comprising a DC voltage divider connected with the rectifier DC voltage output and the one or more gate terminals of the MOSFET devices, the DC voltage divider comprising a plurality of resistive arrangements.

17. The bias circuit of claim 16, wherein the number of the resistive arrangements depends on the number of the MOSFET devices.

18. The bias circuit of claim 15, wherein an AC voltage divider is connected between the amplifier output and the rectifier, the AC voltage divider comprising an arrangement in series of a voltage dividing capacitor and a plurality of resistors.

19. The bias circuit of claim 15, wherein the rectifier comprises a diode with a series capacitance.

20. The bias circuit of claim 19, wherein the diode comprises two MOSFET devices connected in series, each MOSFET device comprising a gate terminal and a source terminal connected to each other.

21. The bias circuit of claim 15, further comprising a bias source providing one or more pre-bias voltages.

22. The bias circuit of claim 21, wherein each of the one or more pre-bias voltages is routed to a respective gate of the MOSFET devices.

23. The bias circuit of claim 21, wherein the bias source provides a fixed or controllable DC output voltage.

24. The bias circuit of claim 15, further comprising a plurality of voltage balancing capacitors, each voltage balancing capacitor connecting a respective gate of the MOSFET devices to a reference node.

25. The bias circuit of claim 24, wherein a ratio of a capacitance of each voltage balancing capacitor of the plurality of voltage balancing capacitors to a capacitance of a gate-source capacitor of a respective MOSFET device is chosen such that respective gates of the MOSFET devices experience same voltage levels.

26. The bias circuit of claim 15, wherein the bias circuit is connected to the power amplifier.

27. The bias circuit of claim 26, wherein the power amplifier is a class-E amplifier, the class-E amplifier comprising a load network.

28. The bias circuit of claim 27, further comprising a bias circuit capacitor connecting the power amplifier output to the rectifier.

29. The bias circuit of claim 28 wherein during operation, a combination of the bias circuit capacitor and the load network provides resonance condition when the MOSFET devices are in OFF state.

30. A bias circuit connectable, during operation, to a power amplifier comprising a plurality of MOSFET devices to produce a power amplifier AC output voltage at a power amplifier output, the bias circuit comprising:

one or more rectifiers to rectify the power amplifier AC output voltage to generate one or more bias outputs.

31. The bias circuit of claim 30, further comprising one or more AC voltage dividers each connected between the amplifier output and a respective rectifier, wherein each AC voltage divider comprises an arrangement in series of a bias capacitor with a plurality of resistors.

32. The bias circuit of claim 30, wherein each rectifier comprises a diode in series with a filter, the filter comprising a resistor in parallel with a capacitance.

33. The bias circuit of claim 32, wherein each diode comprises two MOSFET devices connected in a series configuration, each MOSFET device comprising a gate terminal and a source terminal connected to each other.

34. The bias circuit of claim 30, further comprising a second bias source providing one or more pre-bias voltages.

35. The bias circuit of claim 34, wherein the bias source provides a fixed or controllable DC output voltage.

36. The bias circuit of claim 30, further comprising a plurality of voltage balancing capacitors, each voltage balancing capacitor connecting a respective gate of the MOSFET devices to a reference node.

37. The bias circuit of claim 36, wherein a ratio of a capacitance of each voltage balancing capacitor of the plurality of voltage balancing capacitors to a capacitance of a gate-source capacitor of a respective MOSFET device is chosen such that respective gates of the MOSFET devices experience same voltage levels.

38. The bias circuit of claim 30, wherein the bias circuit is connected to the power amplifier.

39. The bias circuit of claim 38, wherein the power amplifier is a class-E amplifier, the class-E amplifier comprising a load network.

40. The bias circuit of claim 39, further comprising a bias circuit capacitor connecting the power amplifier output to the rectifier.

41. The bias circuit of claim 40 wherein during operation, a combination of the bias circuit capacitor and the load network provides a resonance condition when the MOSFET devices are in OFF state.

42. An RF power amplifier for amplifying an input signal comprising:

an amplifier input;

an amplifier output;

a reference node;

a first inductor adapted to connect the amplifier output to a power supply;

a plurality of devices arranged in a cascode configuration between the amplifier output and the reference node;

an output capacitor connected between the amplifier output and the reference node;

an output resonant circuit comprising a second inductor connected in series with a capacitor, the output resonant circuit being connected at one end to the amplifier output and connectable at another end to a load;

a bias circuit comprising;

an RF voltage divider having an RF voltage divider output, the RF voltage divider being connected with the amplifier output on one side and with a shunt capacitor on another side, the shunt capacitor connecting the RF voltage divider to the reference node;

a rectifier circuit having a rectifier circuit output, the rectifier circuit being connected with the RF voltage divider output on one side and with the reference node on another side;

a DC voltage divider comprising a DC voltage divider first end, a DC voltage divider second end and two or more DC voltage divider outputs, wherein

output and the DC voltage divider second end is connected to the reference node.

43. The RF power amplifier of claim 42, wherein the plurality of amplifying devices are a plurality of MOSFET devices each comprising a MOSFET device gate.

44. The RF power amplifier of claim 43, wherein each of the two or more voltage divider outputs is connected to a respective MOSFET device gate through a series resistor.

45. The RF power amplifier of claim 43, wherein each MOSFET device gate is connected with the reference node through a voltage balancing capacitor.

46. The RF power amplifier of claim 42, wherein the RF voltage divider comprises an arrangement in-series of one or more resistors and one or more capacitors.

47. The RF power amplifier of claim 42, wherein the rectifier circuit comprises a diode in series with a capacitor.

48. The RF power amplifier of claim 42, wherein the DC voltage divider comprises two or more resistors connected in series.

49. The RF power amplifier of claim 48, wherein the diode comprises two MOSFET devices connected in a series configuration, wherein each MOSFET device has a gate terminal and a drain terminal connected to each other.

50. The RF power amplifier of claim 42, wherein the DC voltage divider second end is connected to a bias source having a bias source DC output voltage, the bias source providing one or more pre-bias voltages to the amplifying devices.

51. The RF power amplifier of claim 50, wherein the bias source provides a fixed or controllable DC output voltage.

52. An RF power amplifier for an amplifying an input signal comprising:

an amplifier input;

an amplifier output;

a reference node;

a first inductor adapted to connect the amplifier output to a power supply;

a plurality of amplifying devices arranged in a cascode configuration between the amplifier output and the reference node;

an output capacitor connected between the amplifier output and the reference node;

an output resonant circuit comprising a second inductor connected in series with a capacitor, the output resonant circuit being connected at one end to the amplifier output and connectable at another end to a load;

a bias circuit comprising;

a plurality of RF voltage dividers generating a plurality of RF voltage divider outputs;

each RF voltage divider having an RF voltage divider first side and an RF voltage divider second side, the RF voltage divider first side being connected with the amplifier output and the RF voltage divider second side being connected with a shunt capacitor, the shunt capacitor connecting the plurality of the RF voltage dividers to the reference node; and

a plurality of rectifier circuits generating a plurality of rectifier circuit outputs, and each rectifier circuit connecting a respective RF voltage divider output to the reference node.

53. The RF power amplifier of claim 52, wherein the plurality of amplifying devices are a plurality of MOSFET devices each comprising a MOSFET device gate.

54. The RF power amplifier of claim 53, wherein each of the plurality of the rectifier circuit outputs is connected to a respective MOSFET device gate through a respective series resistor.

55. The RF power amplifier of claim 53, wherein each MOSFET device gate is connected to the reference node through a voltage balancing capacitor.

56. The RF power amplifier of claim 52, wherein each RF voltage divider of the plurality of RF voltage dividers comprises an arrangement in-series of one or more resistors and one or more capacitors.

57. The RF power amplifier of claim 52, wherein each rectifier circuit of the plurality of the rectifier circuits comprises a diode in series with a filter, the filter comprising a capacitance in parallel with a resistor.

58. The RF power amplifier of claim 57, wherein the diode comprises two MOSFET devices connected in a series configuration, wherein each MOSFET device has a gate connected to a source thereof.

59. The amplifier of claim 52, wherein a DC bias voltage source is connected to the second side of the plurality of the RF voltage dividers.

60. The amplifier of claim 59, wherein the DC bias voltage provides a fixed or controllable DC output voltage.