METHOD AND DEVICE FOR PROTECTING INFORMATION CONTAINED IN AN INTEGRATED CIRCUIT

• US 20110185110A1
• Filed: 05/30/2008
• Published: 07/28/2011
• Est. Priority Date: 05/30/2007
• Status: Abandoned Application

• Current Assignee: Summit Design Solutions Incorporated
• Original Assignee: Summit Design Solutions Incorporated
• Inventors: Smigelski, Tom, Cotner, Dennis
• Application Number:
  US12/601,981
• Publication Number:
  US 20110185110A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/3202 Scan chain
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Abstract

An integrated circuit and a method of protection of an integrated circuit provides for a test controller state machine (TCSM) to be coupled to a control structure and/or an input and/or an output of at least one data storage device of the integrated circuit. The TCSM monitors the state of the data storage device and, upon a test request to the integrated circuit, causes the information in the data storage device to be changed or blocked until the data storage device is deemed safe for access. Such an integrated circuit and method protects information contained in data storage devices of the integrated circuit from being revealed during testing of circuitry of the integrated circuit.

Claims

1. A method of protecting information contained in an integrated circuit (IC) from being revealed unless or until the information is changed or otherwise deemed safe for access, the integrated circuit having a test controller state machine (TCSM) directly or indirectly coupled to control structure and/or input and/or output of at least one data storage device, the at least one data storage device having information stored therein and the IC having at least one normal functional mode of operation and at least one testing mode of operation, comprising the steps of:

(a) coupling, directly or indirectly, the TCSM with the integrated circuit to control and/or observe test structures of the integrated circuit,

(b) causing the TCSM upon a request to test the integrated circuit to enter an erase mode, and

(c) performing during the erase mode, either individually, sequentially, or concurrently, one or more of the following steps;

(1) activating a built in self-test (BIST) on one or more of the data storage devices until the information in the data storage device has been deemed safe for access, and/or (2) changing the information in one or more of the data storage device until the information in the data storage device has been deemed safe for access, and/or (3) changing the information contained in any scan cells of the integrated circuit until any information in the scan cells has been erased or deemed safe for access.

2. The method of claim 1 including a step of verifying that the information in the data storage device and/or the scan cells has been changed or deemed safe for access before allowing a safe mode for testing of the integrated circuit.

3. The method of claim 2 further including a step of entering the TCSM into a safe mode and causing the integrated circuit to enter a safe mode for testing.

4. The method of claim 2 including a step of verifying the changing of the information by using a repeatable timed cycle monitored by the TCSM which does not allow commencement of the safe mode for testing until information in at least one of the data storage device or the scan cells has been erased or deemed safe for access.

5. The method of claim 2 wherein the step of verifying that the information has been erased or deemed safe for access includes a step of performing a read operation, to prevent commencement of the safe mode for testing until the information in the data storage device or the scan cells has been erased or deemed safe for access.

6. The method of claim 2 wherein the step of verifying includes a step of waiting a predetermined amount of time before the TCSM will allow commencement of the safe mode for testing until information in the data storage device or the scan cells has been erased or deemed safe for access.

7. The method of claim 1 including the step of causing the TCSM to be a finite state machine or a finite state automaton for providing a model of behavior composed of a finite number of states, transitions between the states, and actions.

8. The method of claim 1 including a step of preventing the TCSM from being a part of any scan chain.

9. The method of claim 1 including a step of selecting the data storage device from the group consisting of random access memory (RAM), read only memory (ROM), higher-level cells, logic registers, non-volatile memory (NVM), Flash, EPROM, and EEPROM.

10. The method of claim 1 wherein the step of performing includes a clearing, resetting, writing over, shifting out, obliterating, destroying, or blocking of the information while outputs are blocked from outside access.

11. The method of claim 10 wherein the writing over is done more than once.

12. The method of claim 11 wherein the writing over done more than once is performed with different or random patterns.

13. The method of claim 1 further including the step of accessing the information during the test mode by direct access, boundary multiplexing, and/or joint test action group (JTAG).

14. An integrated circuit comprising:

(a) at least one data storage device wherein said data storage device has information stored therein and the integrated circuit has at least one normal functional mode of operation and at least one testing mode of operation, and

(b) a test controller state machine (TCSM) directly or indirectly coupled to at least one data storage device wherein the TCSM includes implementation means for causing the information in the at least one data storage device to be protected from outside access unless or until the at least one data storage device is deemed safe for access.

15. The integrated circuit according to claim 14 wherein the TCSM includes means for preventing an output of the data storage device until the information contained therein is fully changed or deemed safe for access.

16. The integrated circuit according to claim 14 wherein the data storage device includes a built-in means for self-testing the data storage device.

17. The integrated circuit according to claim 14 wherein the at least one data storage device is random access memory (“

RAM”

).

18. The integrated circuit according to claim 17 wherein the TCSM includes means for preventing access to the RAM until the self-test has changed the information stored on the RAM.

19. The integrated circuit according to claim 14 wherein the TCSM includes means for causing the at least one data storage device to erase information stored therein.

20. The integrated circuit according to claim 14 wherein the TCSM includes means for causing the at least one data storage device to write over the information contained therein.

21. The integrated circuit according to claim 14 wherein the TCSM includes means for causing the at least one data storage device to shift out the information contained therein.

22. The integrated circuit according to claim 14 wherein the at least one data storage device has non-volatile memory.

23. The integrated circuit according to claim 14 wherein said at least one data storage device is selected from the group consisting of random access memory (RAM), read only memory (ROM), higher-level cell, logic register, non-volatile memory (NVM), Flash, EPROM, and EEPROM.

24. The integrated circuit according to claim 14 wherein the TCSM includes a timing means for allowing enough time to expire such that the stored information is completely erased.

25. The integrated circuit according to claim 14 wherein the TCSM includes:

(a) a timing means for allowing enough time to expire such that the stored information is erased, and

(b) additionally includes a verifying means for verifying that the information was actually erased.

26. The integrated circuit according to claim 14 wherein the TCSM includes a counting means for allowing enough clock cycles to expire such that the stored information is clocked out or otherwise deemed safe for access.

27. The integrated circuit according to claim 14 wherein the TCSM includes means for changing the information contained on the at least one data storage device by erasure, overriding, destroying, shifting out, blocking or clearing.

28. The integrated circuit according to claim 14 wherein the TCSM includes means for observing the information contained on the at least one data storage device by direct access, boundary multiplexing, and/or joint test action group (JTAG).