SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20110215317A1
• Filed: 03/01/2011
• Published: 09/08/2011
• Est. Priority Date: 03/08/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: GODO, Hiromichi, YAMAZAKI, Shunpei
• Granted Patent: US 8,664,653 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Disclosed is a semiconductor device including an insulating layer, a source electrode and a drain electrode embedded in the insulating layer, an oxide semiconductor layer in contact with the insulating layer, the source electrode, and the drain electrode, a gate insulating layer covering the oxide semiconductor layer, and a gate electrode over the gate insulating layer. The upper surface of the surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less. There is a difference in height between an upper surface of the insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode. The difference in height is preferably 5 nm or more. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.

Claims

1. A semiconductor device comprising:

an insulating layer;

a source electrode and a drain electrode embedded in the insulating layer;

an oxide semiconductor layer over and in contact with the insulating layer, the source electrode, and the drain electrode;

a gate insulating layer over the oxide semiconductor layer; and

a gate electrode over the gate insulating layer,

wherein a difference in height exists between an upper surface of the insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode.

2. The semiconductor device according to claim 1, wherein the upper surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square roughness of 1 nm or less.

3. The semiconductor device according to claim 1, wherein the difference in height between the upper surface of the insulating layer and each of the upper surface of the source electrode and the upper surface of the drain electrode is 5 nm or more.

4. The semiconductor device according to claim 1, wherein the difference in height between the upper surface of the insulating layer and each of the upper surface of the source electrode and the upper surface of the drain electrode is 20 nm or less.

5. A semiconductor device comprising:

a first transistor; and

a second transistor over the first transistor,

wherein the first transistor comprises;

a first channel formation region;

a first gate insulating layer over the first channel formation region;

a first gate electrode over the first gate insulating layer so as to overlap with the first channel formation region; and

a first source electrode and a first drain electrode electrically connected to the first channel formation region,

wherein the second transistor comprises;

a second source electrode and a second drain electrode embedded in an insulating layer;

a second channel formation region over and in contact with the insulating layer, the second source electrode, and the second drain electrode;

a second gate insulating layer over the second channel formation region; and

a second gate electrode over the second gate insulating layer,

wherein a difference in height exists between an upper surface of the insulating layer and each of an upper surface of the second source electrode and an upper surface of the second drain electrode.

6. The semiconductor device according to claim 5, wherein the upper surface of the insulating layer, which is in contact with the second channel formation region, has a root-mean-square roughness of 1 nm or less.

7. The semiconductor device according to claim 5, wherein the difference in height between the upper surface of the insulating layer and each of the upper surface of the second source electrode and the upper surface of the second drain electrode is 5 nm or more.

8. The semiconductor device according to claim 5, wherein the difference in height between the upper surface of the insulating layer and each of the upper surface of the second source electrode and the upper surface of the second drain electrode is 20 nm or less.

9. The semiconductor device according to claim 5, wherein the second channel formation region comprises an oxide semiconductor layer.

10. The semiconductor device according to claim 5, wherein the upper surface of the second source electrode and the upper surface of the second drain electrode are partly covered with the insulating layer.

11. A memory device including the semiconductor device according to claim 5.

12. A method for manufacturing a semiconductor device, comprising the steps of:

forming a source electrode and a drain electrode over a substrate;

forming a first insulating layer so as to cover the source electrode and the drain electrode;

performing planarization treatment on a surface of the first insulating layer, thereby forming a second insulating layer having a planarized surface;

forming openings reaching the source electrode and the drain electrode in the second insulating layer, so that a difference in height between the planarized surface of the second insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode is formed;

forming an oxide semiconductor layer over and in contact with the second insulating layer, the source electrode, and the drain electrode;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer.

13. The method for manufacturing a semiconductor device according to claim 12, wherein the planarization treatment is performed so that a root-mean-square roughness of the planarized surface is 1 nm or less.

14. The method for manufacturing a semiconductor device according to claim 12, wherein the difference in height between the planarized surface of the second insulating layer and each of the upper surface of the source electrode and the upper surface of the drain electrode is 5 nm or more.

15. The method for manufacturing a semiconductor device according to claim 12, wherein the difference in height between the planarized surface of the second insulating layer and each of the upper surface of the source electrode and the upper surface of the drain electrode is 20 nm or less.

16. The method for manufacturing a semiconductor device according to claim 12, wherein the openings are formed so that the upper surface of the source electrode and the upper surface of the drain electrode are partly covered with the second insulating layer.

17. A method for manufacturing a semiconductor device, comprising the steps of:

forming a source electrode and a drain electrode over a substrate;

forming a first insulating layer so as to cover the source electrode and the drain electrode;

performing planarization treatment on a surface of the first insulating layer, thereby forming a second insulating layer having a planarized surface and exposing the source electrode and the drain electrode;

thinning the source electrode and the drain electrode so that a difference in height between the planarized surface of the second insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode is formed;

forming an oxide semiconductor layer over and in contact with the second insulating layer, the source electrode, and the drain electrode;

forming a gate insulating layer over the oxide semiconductor layer; and

forming a gate electrode over the gate insulating layer.

18. The method for manufacturing a semiconductor device according to claim 17, wherein the planarization treatment is performed so that a root-mean-square roughness of the planarized surface is 1 nm or less.

19. The method for manufacturing a semiconductor device according to claim 17, wherein the difference in height between the planarized surface of the second insulating layer and each of the upper surface of the source electrode and the upper surface of the drain electrode is 5 nm or more.

20. The method for manufacturing a semiconductor device according to claim 17, wherein the difference in height between the planarized surface of the second insulating layer and each of the upper surface of the source electrode and the upper surface of the drain electrode is 20 nm or less.

21. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first transistor comprising a channel formation region, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, overlapping with the channel formation region, and a first source electrode and a first drain electrode electrically connected to the channel formation region;

forming a first insulating layer over the first transistor;

forming a second source electrode and a second drain electrode over a surface of the first insulating layer;

forming a second insulating layer so as to cover the second source electrode and the second drain electrode;

performing planarization treatment on a surface of the second insulating layer, thereby forming a third insulating layer having a planarized surface;

forming openings reaching the second source electrode and the second drain electrode in the third insulating layer, so that a difference in height between the planarized surface of the third insulating layer and each of an upper surface of the second source electrode and an upper surface of the second drain electrode is formed;

forming an oxide semiconductor layer over and in contact with the third insulating layer, the second source electrode, and the second drain electrode;

forming a second gate insulating layer over the oxide semiconductor layer; and

forming a second gate electrode over the second gate insulating layer.

22. The method for manufacturing a semiconductor device according to claim 21, wherein the planarization treatment is performed so that a root-mean-square roughness of the planarized surface of the third insulating layer is 1 nm or less.

23. The method for manufacturing a semiconductor device according to claim 21, wherein the difference in height between the planarized surface of the third insulating layer and each of the upper surface of the second source electrode and the upper surface of the second drain electrode is 5 nm or more.

24. The method for manufacturing a semiconductor device according to claim 21, wherein the difference in height between the planarized surface of the third insulating layer and each of the upper surface of the second source electrode and the upper surface of the second drain electrode is 20 nm or less.

25. The method for manufacturing a semiconductor device according to claim 21, wherein the openings are formed so that the upper surface of the second source electrode and the upper surface of the second drain electrode are partly covered with the second insulating layer.

26. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first transistor comprising a channel formation region, a first gate insulating layer over the channel formation region, a first gate electrode over the first gate insulating layer, overlapping with the channel formation region, and a first source electrode and a first drain electrode electrically connected to the channel formation region;

forming a first insulating layer over the first transistor;

forming a second source electrode and a second drain electrode over a surface of the first insulating layer;

forming a second insulating layer so as to cover the second source electrode and the second drain electrode;

performing planarization treatment on a surface of the second insulating layer, thereby forming a third insulating layer having a planarized surface and exposing the second source electrode and the second drain electrode;

thinning the second source electrode and the second drain electrode so that a difference in height between the planarized surface of the third insulating layer and each of an upper surface of the second source electrode and an upper surface of the second drain electrode is formed;

forming an oxide semiconductor layer over and in contact with the third insulating layer, the second source electrode, and the second drain electrode;

forming a second gate insulating layer over the oxide semiconductor layer; and

forming a second gate electrode over the second gate insulating layer.

27. The method for manufacturing a semiconductor device according to claim 26, wherein the planarization treatment is performed so that a root-mean-square roughness of the planarized surface of the third insulating layer is 1 nm or less.

28. The method for manufacturing a semiconductor device according to claim 26, wherein the difference in height between the planarized surface of the third insulating layer and each of the upper surface of the second source electrode and the upper surface of the second drain electrode is 5 nm or more.

29. The method for manufacturing a semiconductor device according to claim 26, wherein the difference in height between the planarized surface of the third insulating layer and each of the upper surface of the second source electrode and the upper surface of the second drain electrode is 20 nm or less.