Semiconductor device and method for manufacturing semiconductor device

• US 8,664,653 B2
• Filed: 03/01/2011
• Issued: 03/04/2014
• Est. Priority Date: 03/08/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Godo, Hiromichi
• Primary Examiner(s): Lam, Cathy N
• Application Number:
  US13/037,545
• Publication Number:
  US 20110215317A1
• Time in Patent Office: 1,099 Days
• Field of Search: 257/43, 257/E29.255, 257/E27.06, 257/E21.46, 257/347, 257/57, 257/72, 257/646, 438/104, 438/412, 438/722, 438/151, 438/157, 438/795
• US Class Current: 257/43
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Disclosed is a semiconductor device including an insulating layer, a source electrode and a drain electrode embedded in the insulating layer, an oxide semiconductor layer in contact with the insulating layer, the source electrode, and the drain electrode, a gate insulating layer covering the oxide semiconductor layer, and a gate electrode over the gate insulating layer. The upper surface of the surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less. There is a difference in height between an upper surface of the insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode. The difference in height is preferably 5 nm or more. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.

Claims

1. A processor comprising:

a register array;

an arithmetic logic unit operationally connected to the register array; and

an instruction register operationally connected to the arithmetic logic unit,

wherein at least one of the register array, the arithmetic logic unit and the instruction register comprises a first transistor and a second transistor over the first transistor,

wherein a channel formation region of the first transistor comprises silicon,

wherein a channel formation region of the second transistor comprises an oxide semiconductor, and

wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor.

2. The processor according to claim 1,

wherein the source electrode and the drain electrode of the second transistor are embedded in an insulating layer, and

wherein a difference in height exists between an upper surface of the insulating layer and upper surfaces of the source electrode and the drain electrode of the second transistor.

3. The processor according to claim 2,

wherein the upper surface of the insulating layer is in contact with the channel formation region of the second transistor, and

wherein the upper surface of the insulating layer has a root-mean-square roughness of 1 nm or less.

4. The processor according to claim 2,

wherein the difference in height between the upper surface of the insulating layer and the upper surfaces of the source electrode and the drain electrode of the second transistor is 5 nm or more.

5. The processor according to claim 2,

wherein the difference in height between the upper surface of the insulating layer and the upper surfaces of the source electrode and the drain electrode of the second transistor is 20 nm or less.

6. The processor according to claim 2,

wherein the upper surfaces of the source electrode and the drain electrode of the second transistor are partly covered with the insulating layer.

7. The processor according to claim 1,

wherein the processor is a CPU.

8. The processor according to claim 1, further comprising:

a silicon substrate, wherein the channel formation region of the first transistor is formed in the silicon substrate; and

an insulating layer over the first transistor, wherein the second transistor is formed over the insulating layer.

9. The processor according to claim 1, further comprising:

an insulating substrate, wherein the first transistor comprises a semiconductor layer comprising the channel formation region, and wherein the semiconductor layer is formed over the insulating substrate; and

an insulating layer over the first transistor, wherein the second transistor is formed over the insulating layer.

10. A processor comprising:

a register array;

an arithmetic logic unit operationally connected to the register array; and

an instruction register operationally connected to the arithmetic logic unit,

wherein at least one of the register array, the arithmetic logic unit and the instruction register comprises a first transistor and a second transistor over the first transistor,

wherein a channel formation region of the first transistor comprises silicon,

wherein a channel formation region of the second transistor comprises an oxide semiconductor,

wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, and

wherein a gate electrode of the second transistor is formed over the channel formation region of the second transistor.

11. The processor according to claim 10,

wherein the source electrode and the drain electrode of the second transistor are embedded in an insulating layer, and

wherein a difference in height exists between an upper surface of the insulating layer and upper surfaces of the source electrode and the drain electrode of the second transistor.

12. The processor according to claim 11,

wherein the upper surface of the insulating layer is in contact with the channel formation region of the second transistor, and

wherein the upper surface of the insulating layer has a root-mean-square roughness of 1 nm or less.

13. The processor according to claim 11,

wherein the difference in height between the upper surface of the insulating layer and the upper surfaces of the source electrode and the drain electrode of the second transistor is 5 nm or more.

14. The processor according to claim 11,

wherein the difference in height between the upper surface of the insulating layer and the upper surfaces of the source electrode and the drain electrode of the second transistor is 20 nm or less.

15. The processor according to claim 11,

wherein the upper surfaces of the source electrode and the drain electrode of the second transistor are partly covered with the insulating layer.

16. The processor according to claim 10,

wherein the processor is a CPU.

17. The processor according to claim 10, further comprising:

a silicon substrate, wherein the channel formation region of the first transistor is formed in the silicon substrate; and

an insulating layer over the first transistor, wherein the second transistor is formed over the insulating layer.

18. The processor according to claim 10, further comprising:

an insulating substrate, wherein the first transistor comprises a semiconductor layer comprising the channel formation region, and wherein the semiconductor layer is formed over the insulating substrate; and

an insulating layer over the first transistor, wherein the second transistor is formed over the insulating layer.