COMMAND INTERFACE SYSTEMS AND METHODS

• US 20110302328A1
• Filed: 08/19/2011
• Published: 12/08/2011
• Est. Priority Date: 08/16/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ito, Yutaka, Yamamoto, Tadashi
• Granted Patent: US 8,572,292 B2
• Time in Patent Office: Days
• US Class Current: 710/5
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling

Abstract

Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed.

Claims

1. A method comprising:

executing commands in an electronic device during a first mode of operation of the electronic device;

suspending execution of commands during a transfer period between the first mode of operation and a second mode of operation of the electronic device; and

resuming the execution of commands in the electronic device during the second mode of operation of the electronic device following the transfer period.

2. The method of claim 1, wherein executing commands in an electronic device during a first mode of operation further comprises:

decoding internal command signals into internal commands in a command decoder in a memory device; and

executing the internal commands during the first mode of operation of the memory device, the first mode of operation being a sleep mode of operation of the memory device.

3. The method of claim 1, further comprising:

receiving external command signals in the electronic device to indicate an end of the first mode of operation.

4. The method of claim 1, wherein resuming the execution of commands in the electronic device during the second mode of operation further comprises:

decoding external command signals into external commands in a command decoder in a memory device; and

executing the external commands during the second mode of operation of the memory device, the second mode of operation being a normal mode of operation of the memory device.

5. The method of claim 1, wherein suspending execution of commands includes suspending execution of commands when a chip select signal operates to disable a command decoder in the electronic device.

6. A method comprising:

executing first commands with a command decoder in an electronic device;

disabling the command decoder during a transfer period; and

executing second commands with the command decoder in the electronic device following the transfer period.

7. The method of claim 6, further comprising generating the first commands in the electronic device, the first commands being internal commands.

8. The method of claim 7, wherein executing first commands includes executing the internal commands with the command decoder in the electronic device before the transfer period.

9. The method of claim 6, further comprising receiving the second commands in the electronic device, the second commands being external commands.

10. The method of claim 9, wherein executing second commands includes executing the external commands with the command decoder in the electronic device following the transfer period.

11. An apparatus comprising:

a command decoder in an electronic device to decode and execute commands within the electronic device during a first mode of operation and during a second mode of operation; and

a controller to generate a disable command to disable the command decoder during a transfer period between the first mode of operation and the second mode of operation.

12. The apparatus of claim 11, wherein the controller is structured to generate the commands executed by the command decoder during the first mode of operation, the commands being internal commands.

13. The apparatus of claim 12, wherein the controller comprises an error correcting code controller circuit to generate internal command signals during the first mode of operation, the command decoder to decode the internal command signals into the internal commands.

14. The apparatus of claim 11, further comprising a circuit to generate an internal chip select signal to disable the command decoder during the transfer period.

15. A memory device comprising:

an array of memory cells;

a command decoder to decode and execute commands with respect to the memory cells in the array; and

a controller to suspend the execution of commands during a transfer period between a period of operation of the memory device according to a first mode of operation and a period of operation of the memory device according to a second mode of operation.

16. The memory device of claim 15, wherein the controller is structured to generate a disable command to disable the command decoder during the transfer period.

17. The memory device of claim 16, wherein the controller is coupled to the command decoder to generate a chip select signal during the transfer period to disable the command decoder.

18. The memory device of claim 15, wherein the controller comprises an error correcting code controller circuit coupled to generate internal command signals during the first mode of operation.

19. The memory device of claim 15, wherein:

the first mode of operation comprises a sleep mode of operation; and

the second mode of operation comprises a normal mode of operation.

20. The memory device of claim 15, further comprising a state machine to generate control signals to control operations of the memory device during the first mode of operation.

21. A method comprising:

executing commands in an electronic device during operation of the electronic device; and

suspending the execution of commands in the electronic device when changing to a different mode of operation of the electronic device.

22. The method of claim 21, further comprising:

generating internal commands in the electronic device during a sleep mode of operation; and

executing the internal commands during the sleep mode of operation of the electronic device.

23. The method of claim 22, further comprising:

receiving external commands in the electronic device during a normal mode of operation; and

executing the external commands during the normal mode of operation of the electronic device.

24. The method of claim 23, wherein suspending the execution of commands includes suspending execution of the internal commands in the electronic device between an end of the sleep mode of operation and a beginning of the normal mode of operation.

25. The method of claim 24, wherein the electronic device comprises a memory device.