GENERATION OF ADJUSTABLE PHASE REFERENCE WAVEFORM

• US 20120112811A1
• Filed: 02/19/2010
• Published: 05/10/2012
• Est. Priority Date: 02/19/2010
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Cook, David M.
• Granted Patent: US 8,653,873 B2
• Time in Patent Office: Days
• US Class Current: 327/175
• CPC Class Codes: H03K 2005/00286 Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

One embodiment provides a system for generating a reference waveform. The system can include a first pulse-width modulation (PWM) channel configured to provide a first PWM waveform having a first duty cycle and a first frequency. A second PWM channel is configured to provide a second PWM waveform having a second duty cycle and the first frequency. Combinational logic is configured to combine the first PWM waveform and the second PWM waveform to generate a phase-shifted reference PWM waveform having the first frequency and a phase shift that is based on the first duty cycle and the second duty cycle.

Claims

1. A system comprising:

a first pulse-width modulation (PWM) channel configured to provide a first PWM waveform having a first duty cycle and a first frequency;

a second PWM channel configured to provide a second PWM waveform having a second duty cycle and the first frequency; and

combinational logic configured to combine the first PWM waveform and the second PWM waveform to generate a phase-shifted reference PWM waveform having the first frequency and a phase shift that is based on the first duty cycle and the second duty cycle.

2. The system of claim 1, wherein the combinational logic comprises at least one exclusive-OR gate configured to provide the phase-shifted reference PWM waveform based on the first PWM waveform and the second PWM waveform.

3. The system of claim 1, wherein the combinational logic comprises an inverter configured to increase an adjustable range for the phase shift.

4. The system of claim 3, wherein the inverter comprises a second exclusive-OR gate, the second exclusive-OR gate being configured to invert the phase-shifted reference PWM waveform based on a sign input set to one of invert or not invert the phase-shifted reference PWM waveform.

5. The system of claim 1, further comprising a third PWM channel configured to provide a carrier PWM waveform having a fixed duty cycle and the first frequency, the phase shift of the phase-shifted reference PWM waveform being relative to the carrier PWM waveform, the phase-shifted reference PWM waveform also having the fixed duty cycle.

6. The system of claim 5, wherein each of the first PWM channel, the second PWM channel and the third PWM channel correspond to PWM channels in a microprocessor.

7. The system of claim 6, further comprising:

circuitry that is excited in response to the carrier PWM waveform and is configured to provide an output signal at the frequency of the carrier PWM waveform; and

a demodulator configured to demodulate the output signal based on the phase-shifted reference PWM waveform and provide a corresponding demodulated output signal.

8. The system of claim 7, wherein the phase shift of the phase-shifted reference PWM waveform is set according to a phase difference between the carrier PWM waveform and the output signal.

9. The system of claim 7, wherein the circuitry comprises a micro-electrical-mechanical system.

10. The system of claim 1, further comprising:

a first duty adjustor configured to adjust the first duty cycle of the first PWM waveform; and

a second duty adjustor configured to adjust the second duty cycle of the second PWM waveform.

11. The system of claim 10, wherein each of the first duty adjustor and the second duty adjustor comprises a respective duty register configured to store a programmable value that sets the duty cycle for each of the first PWM waveform and the second PWM waveform.

12. A method for generating a reference waveform comprising:

generating a first pulse-width modulation (PWM) waveform;

generating a second PWM waveform;

exclusive-ORing the first PWM waveform and the second PWM waveform to provide the reference waveform, the reference waveform having a phase shift relative to a carrier waveform that is adjustable based on a duty cycle of the first PWM waveform and the second PWM waveform.

13. The method of claim 12, further comprising adjusting the duty cycle of the first PWM waveform and the second PWM waveform to adjust the phase shift of the reference waveform.

14. The method of claim 12, wherein each of the first PWM waveform and the second PWM waveform is generated by a PWM module in a microprocessor, the method further comprising setting the duty cycle for each of the first PWM waveform and the second PWM waveform by programming a duty value in respective duty registers.