THERMO PROGRAMMABLE RESISTOR BASED ROM

• US 20120170352A1
• Filed: 12/29/2010
• Published: 07/05/2012
• Est. Priority Date: 12/29/2010
• Status: Active Grant

• Current Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Inventors: Le Neel, Olivier, Jimenez, Jean
• Granted Patent: US 9,159,413 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/008 Write by generating heat in the surroundings of the memory material, e.g. thermowrite
• CPC Class Codes: G11C 2213/33 Material including silicon
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8613 Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/884 Other compounds of groups 13-15, e.g. elemental or compound semiconductors

Abstract

An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has an adjustable resistor and a heating element. A dielectric material separates the heating element from the adjustable resistor. The heating element alters the resistance of the resistor by applying heat thereto. The magnitude of the resistance of the adjustable resistor represents the value of data stored in the memory cell.

Claims

1. An integrated circuit comprising:

a semiconductor substrate;

a first dielectric layer overlying the substrate;

an adjustable resistor overlying the first dielectric layer, a resistance of the adjustable resistor being representative of a value of data stored in the adjustable resistor;

a heating element adjacent the adjustable resistor and configured to write data to the adjustable resistor; and

a second dielectric layer between the adjustable resistor and the heating element.

2. The integrated circuit of claim 1 wherein the heating element is configured to dissipate heat through the second dielectric layer to write data to the adjustable resistor.

3. A memory cell comprising:

a thin film adjustable resistor;

a thin film heating element adjacent the adjustable resistor; and

a dielectric layer separating the thin film adjustable resistor from the thin film heating element, the thin film heating element configured to write data to the thin film adjustable resistor by dissipating heat through the dielectric layer to the thin film adjustable resistor.

4. The memory cell of claim 3 wherein the thin film adjustable resistor is chromium silicon.

5. A memory array comprising:

a plurality of memory cells arranged in rows and columns of memory cells, each memory cell respectively including;

a thin film adjustable resistor; and

a thin film heating element configured to write data to the adjustable resistor;

a plurality of bitlines, each bitline coupled to a respective column of memory cells;

a plurality of wordlines, each wordline coupled to a respective row of memory cells; and

a plurality of heater lines, each heater line coupled to a respective row of memory cells, each row of memory cells being coupled to a respective heater line and a respective word line.

6. The memory array of claim 5 wherein each heater line is connected to the heating elements of a respective row of memory cells and configured to pass a current through a selected heating element of the respective row of memory cells to write data to a selected adjustable resistor of the respective row of heating elements.

7. A device comprising:

a first thin film layer of chromium silicon having a first concentration of silicon;

a second thin film layer of chromium silicon in contact with the first layer of chromium silicon; and

a thin film heating element adjacent the first and second thin film layers of chromium silicon and configured to write data to the first thin film layer of chromium silicon by heat transfer.

8. The device of claim 7 wherein the heating element is configured to write data to the first and second thin film layers of chromium silicon by semi-permanently altering a resistance of the first thin film layer of chromium silicon.

9. A device comprising:

a semiconductor substrate;

a control circuit in the semiconductor substrate;

a first dielectric layer above the semiconductor substrate; and

a first array of memory cells above the first dielectric layer, each memory cell of the first array respectively including;

an adjustable resistor; and

a heating element separated from the adjustable resistor by a second dielectric layer, the heating element configured to write data to the adjustable resistor by heat transfer.

10. The device of claim 9 wherein each memory cell of the first array of memory cells is a multi-bit memory cell.

11. A method comprising:

forming control circuitry in a semiconductor substrate;

forming a dielectric layer above the semiconductor substrate;

forming a thin film adjustable resistor in the dielectric layer;

forming a heating element adjacent the adjustable resistor;

forming a second dielectric layer separating the heating element from the thin film adjustable resistor; and

storing data in the adjustable resistor by heating the adjustable resistor to alter a resistance of the adjustable resistor.

12. The method of claim 11 wherein forming the adjustable resistor comprises:

forming a first layer of resistive material; and

forming a second layer of resistive material directly in contact with the first layer, the first and second layers forming the adjustable resistor.

13. A method comprising:

passing a current through a first thin film resistor;

dissipating heat from the first thin film resistor through a dielectric layer to a second thin film resistor to store data in the second thin film resistor; and

reading data from the second thin film resistor by obtaining an indication of a resistance of the second thin film resistor.

14. The method of claim 13 wherein the step of reading data comprises comparing a resistance of the second thin film resistor to a resistance of a third thin film resistor.

15. A memory comprising:

a substrate;

first metal interconnection lines at a first level above the substrate;

second metal interconnection lines at a second level above the first level;

a first array of memory cells at the second level; and

a plurality of wordlines formed of the second metal interconnection lines, each wordline connected to a respective row of memory cells of the first array of memory cells.

16. The memory of claim 15, further comprising:

a third set of metal interconnection lines at a third level above the substrate; and

a second array of memory cells at the third level above the substrate.

17. A memory cell comprising:

a first thin film resistive layer;

a source layer in contact with the first thin film resistive layer;

a dielectric layer adjacent the first thin film resistive layer; and

a second thin film resistive layer of refractory metal adjacent the dielectric layer, the second thin film resistive layer being configured to dissipate heat through the dielectric layer to the first thin film resistive layer and the source layer to write data to the first thin film resistive layer by causing a migration of atoms from the source layer to the first thin film resistive layer.

18. The memory cell of claim 17 wherein the first thin film resistive layer is a first chromium silicon alloy having a first concentration of silicon.

19. The memory cell of claim 18 wherein the source layer comprises silicon.

20. An integrated circuit comprising:

an adjustable thin film resistor coupled to and extending between a first metal interconnection line and a second metal interconnection line;

a thin film heating element adjacent the thin film adjustable resistor, the thin film heating element being coupled to and extending between a third metal interconnection line and a fourth metal interconnection line; and

a dielectric layer separating the adjustable thin film resistor from the thin film heating element, the thin film heating element configured to write data to the adjustable thin film resistor by dissipating heat to the adjustable resistor through the dielectric layer.

21. The integrated circuit of claim 20 wherein the first and third metal interconnection lines connect to a bitline, the second metal interconnection line connects to a wordline, and the fourth metal interconnection line connects to a heater line configured to pass a current through the heating element.