Thermo programmable resistor based ROM

• US 9,159,413 B2
• Filed: 12/29/2010
• Issued: 10/13/2015
• Est. Priority Date: 12/29/2010
• Status: Active Grant

• Current Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Pte Limited (STMicroelectronics NV)
• Inventors: Le Neel, Olivier, Jimenez, Jean
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US12/981,379
• Publication Number:
  US 20120170352A1
• Time in Patent Office: 1,749 Days
• Field of Search: 365/148, 438/384, 257/2, 257/E21.004, 257/E45.001
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2013/008 Write by generating heat in the surroundings of the memory material, e.g. thermowrite
• CPC Class Codes: G11C 2213/33 Material including silicon
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8613 Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel
• CPC Class Codes: H10N 70/881 Switching materials
• CPC Class Codes: H10N 70/884 Other compounds of groups 13-15, e.g. elemental or compound semiconductors

Abstract

An integrated circuit is formed having an array of memory cells located in the dielectric stack above a semiconductor substrate. Each memory cell has an adjustable resistor and a heating element. A dielectric material separates the heating element from the adjustable resistor. The heating element alters the resistance of the resistor by applying heat thereto. The magnitude of the resistance of the adjustable resistor represents the value of data stored in the memory cell.

Claims

1. An integrated circuit comprising:

a semiconductor substrate;

a first dielectric layer overlying the substrate;

an adjustable resistor overlying the first dielectric layer, a resistance of the adjustable resistor being representative of a value of digital data stored in the adjustable resistor;

a heating element adjacent the adjustable resistor and writing digital data to the adjustable resistor;

a second dielectric layer between the adjustable resistor and the heating element;

a bit line in ohmic electrical connection with both the adjustable resistor and the heating element and providing the value of the digital data during a data read cycle of the adjustable resistor;

a word line in ohmic electrical connection with the adjustable resistor; and

a heater line in ohmic electrical connection with the heating element, the heater line being different from the word line and the bit line.

2. The integrated circuit of claim 1 wherein the heating element dissipates heat through the second dielectric layer to write digital data to the adjustable resistor.

9. The integrated circuit of claim 1 wherein a first region of the heating element adjacent the adjustable resistor is narrower than a second region of the heating element not adjacent the adjustable resistor.

3. A memory cell comprising:

a thin film adjustable resistor;

a thin film heating element adjacent the thin film adjustable resistor;

a dielectric layer separating the thin film adjustable resistor from the thin film heating element, the thin film heating element writing digital data to the thin film adjustable resistor by dissipating heat through the dielectric layer to the thin film adjustable resistor;

a bit line in ohmic electric connection with both the thin film adjustable resistor and the thin film heating element and providing a value of the digital data during a read cycle of the memory cell;

a word line in ohmic electrical connection with the thin film adjustable resistor; and

a heater line in ohmic electrical connection with the thin film heating element, the heater line being different from the word line and the bit line.

4. The memory cell of claim 3 wherein the thin film adjustable resistor is chromium silicon.

10. The memory cell of claim 3 wherein a first region of the thin film heating element adjacent the thin film adjustable resistor is narrower than a second region of the thin film heating element not adjacent the thin film adjustable resistor.

5. A device comprising:

a semiconductor substrate;

a control circuit in the semiconductor substrate;

a first dielectric layer above the semiconductor substrate; and

a first array of memory cells above the first dielectric layer, each memory cell of the first array respectively including;

an adjustable resistor; and

a heating element separated from the adjustable resistor by a second dielectric layer, the heating element writing digital data to the adjustable resistor by heat transfer; and

a plurality of bit lines, each in ohmic electrical connection with both an adjustable resistor and a heating element of a respective memory cell;

a plurality of word lines, each in ohmic electrical connection with the adjustable resistor of one of the memory cells; and

a plurality of heater lines, each in ohmic electrical connection with a heating element, the heater lines being different from the word lines and the bit lines.

6. The device of claim 5 wherein each memory cell of the first array of memory cells is a multi-bit memory cell.

7. The device of claim 5 wherein, for each memory cell of the first array of memory cells, a first region of the heating element adjacent the adjustable resistor is narrower than a second region of the heating element not adjacent the adjustable resistor.

8. The device of claim 5 wherein the first dielectric layer has a first thermal conductivity and the second dielectric layer has a second thermal conductivity greater than the first thermal conductivity.