CLOCK STRETCHER FOR VOLTAGE DROOP MITIGATION
First Claim
1. A device comprising:
- a multiplexer to receive a plurality of phase shifted versions of a clock signal and to output one of the plurality of phase shifted versions of the clock signal as an output clock signal; and
a control component to control, in response to a voltage droop event signal indicating an occurrence of a voltage droop event in a power supply, the multiplexer to iteratively select the plurality of phase shifted versions of the clock signal to reduce a frequency of the output clock signal and to statically select one of the phase shifted versions of the clock signal, as the output clock signal, when the voltage droop event signal indicates that the voltage droop event is not occurring.
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Abstract
A clock frequency of a clock signal used by a processor may be temporarily reduced to compensate for voltage droops in the power supply to the processor. A device may include a multiplexer to receive a group of phase shifted versions of the clock signal and to output one of the group of phase shifted versions of the clock signal as an output clock signal. A control component may receive the output clock signal from the multiplexer and a voltage droop event signal indicating whether a voltage droop event is occurring in a power supply. The control component may control, in response to the voltage droop event signal indicating the occurrence of the voltage droop event, the multiplexer to iteratively select the group of phase shifted versions of the clock signal to reduce the frequency of the output clock signal.
62 Citations
19 Claims
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1. A device comprising:
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a multiplexer to receive a plurality of phase shifted versions of a clock signal and to output one of the plurality of phase shifted versions of the clock signal as an output clock signal; and a control component to control, in response to a voltage droop event signal indicating an occurrence of a voltage droop event in a power supply, the multiplexer to iteratively select the plurality of phase shifted versions of the clock signal to reduce a frequency of the output clock signal and to statically select one of the phase shifted versions of the clock signal, as the output clock signal, when the voltage droop event signal indicates that the voltage droop event is not occurring. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method comprising:
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receiving, by a device, a plurality of phase shifted versions of an input clock signal, the input clock signal being used by a processor powered by a power supply; iteratively outputting, by the device, the plurality of phase shifted versions of the input clock signal to generate an output clock signal as a reduced frequency representation of the input clock signal, the iteratively outputting being performed in response to a voltage droop occurring in the power supply; and outputting, by the device, a statically selected one of the plurality of phase shifted versions of the input clock signal as the output clock signal, when the sequentially outputting, in response to the voltage droop, is not being performed. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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19. A system comprising:
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a delay locked loop (DLL) to receive a clock signal and output delayed versions of the clock signal as a plurality of phase shifted versions of the clock signal; a multiplexer to receive the plurality of phase shifted versions of the clock signal and to output one of the plurality of phase shifted versions of the clock signal as an output clock signal, where the output clock signal is used by a processor that is powered from a power supply; a droop detector to generate a voltage droop event signal when a voltage droop occurs in the power supply, the droop detector generating the voltage droop event signal based on a comparison of a phase of one of the delayed versions of the clock signal, as output from the DLL, and a phase of a second delayed version of the clock signal; and a control component to receive the voltage droop event signal, the control component controlling, in response to the voltage droop event signal, the multiplexer to iteratively select the plurality of phase shifted versions of the clock signal to reduce a frequency of the output clock signal and to statically select one of the phase shifted versions of the first clock signal when the voltage droop event is not occurring.
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Specification