INTEGRATED CIRCUIT

• US 20120199937A1
• Filed: 10/21/2010
• Published: 08/09/2012
• Est. Priority Date: 10/22/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Vellianitis, Georgios, Curatola, Gilberto, Fotopoulou, Kyriaki, Akil, Nader
• Granted Patent: US 9,287,414 B2
• Time in Patent Office: Days
• US Class Current: 257/471
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/083 Anode or cathode regions of thyristors or gated bipolar-mode devices
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

An integrated circuit including a Schottky diode, and a method of making the same. The diode includes an active region bordered by an isolation region in a semiconductor substrate of the integrated circuits, a first electrode having a metal contact provided on a surface of the active region, and a second electrode having a silicide contact also provided on the surface of the active region.

Claims

1. An integrated circuit including a Schottky diode, the diode comprising:

an active region bordered by an isolation region in a semiconductor substrate of the integrated circuit;

a first electrode comprising a metal contact provided on a surface of the active region; and

a second electrode comprising a silicide contact also provided on said surface of said active region.

2. The integrated circuit of claim 1, wherein the isolation region comprises shallow trench isolation.

3. The integrated circuit of claim 1, wherein the active region comprises a doped well, and wherein the first and second electrodes are provided on the surface of the active region above the doped well.

4. The integrated circuit of claim 1, wherein:

a portion of the surface of the active region is covered by a protection layer;

the metal contact extends through the protection layer to meet the surface of the active region; and

the silicide contact is provided on an exposed portion of the surface of the active region not covered by the protection layer.

5. The integrated circuit of claim 1, comprising a portion of semiconductor material located in the active region and adjacent the edges of the metal contact of the first electrode, for reducing leakage current at said edges, wherein the portion of semiconductor material is doped to have a conductivity type opposite to that of the remainder of the active region.

6. The integrated circuit of claim 5, wherein portion of semiconductor material adjacent the edges of the metal contact of the first electrode forms a closed ring around the metal contact.

7. The integrated circuit of claim 1, wherein the metal contact of the first electrode comprises a portion of an interconnect level of the substrate.

8. The integrated circuit of claim 7, wherein the interconnect level is a local interconnect level of the substrate.

9. The integrated circuit of claim 7, wherein the interconnect level is a lowest metal interconnect level (M1) of the substrate.

10. An RFID tag including the integrated circuit of claim 1.

11. A method of making an integrated circuit including a Schottky diode, the method comprising:

providing a semiconductor substrate;

providing an isolation region in the substrate, wherein the isolation borders an active region of the substrate;

forming a metal contact on a surface of the active region to provide a first electrode of the diode; and

forming a silicide contact on said surface of said active region to provide a second electrode of the diode.

12. The method of claim 11, comprising:

covering a portion of the surface of the active region with a protection layer;

forming the metal contact of the first electrode such that it extends through the protection layer to meet the surface of the active region; and

forming the silicide contact on an exposed portion of the surface of the active region not covered by the protective layer of semiconductor material.

13. The method of claim 11, comprising:

forming a portion of semiconductor material in the active region corresponding to an intended configuration of the metal contact of the first electrode, wherein the portion of semiconductor material is has a conductivity type opposite to that of the remainder of the active region; and

forming said metal contact such that the portion of semiconductor material is positioned adjacent the edges of the metal contact, for reducing leakage current at said edges.

14. The method of claim 11, comprising forming an interconnect level of the substrate, wherein the metal contact of the first electrode is formed is the same processing step as the formation of the interconnect level.

15. The method of claim 14, wherein the interconnect level is a local interconnect level of the substrate.

16. The method of claim 14, wherein the interconnect level is a lowest metal interconnect level (M1) of the substrate.

17. A method for making an RFID tag, the method including the method of making an integrated circuit including a Schottky diode for making an integrated circuit of the RFID tag, the method comprising:

providing a semiconductor substrate;

providing an isolation region in the substrate, wherein the isolation borders an active region of the substrate;

forming a metal contact on a surface of the active region to provide a first electrode of the diode; and

forming a silicide contact on said surface of said active region to provide a second electrode of the diode.

18. The method of claim 17, comprising:

covering a portion of the surface of the active region with a protection layer;

forming the metal contact of the first electrode such that it extends through the protection layer to meet the surface of the active region; and

forming the silicide contact on an exposed portion of the surface of the active region not covered by the protective layer of semiconductor material.

19. The method of claim 17, comprising:

forming a portion of semiconductor material in the active region corresponding to an intended configuration of the metal contact of the first electrode, wherein the portion of semiconductor material is has a conductivity type opposite to that of the remainder of the active region; and

forming said metal contact such that the portion of semiconductor material is positioned adjacent the edges of the metal contact, for reducing leakage current at said edges.

20. The method of claim 17, comprising forming an interconnect level of the substrate, wherein the metal contact of the first electrode is formed is the same processing step as the formation of the interconnect level.