SHIELDED GATE TRENCH MOSFET DEVICE AND FABRICATION

• US 20120205737A1
• Filed: 04/26/2012
• Published: 08/16/2012
• Est. Priority Date: 08/14/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Chen, John, Lee, Il Kwan, Chang, Hong, Li, Wenjun, Bhalla, Anup, Yilmaz, Hamza
• Granted Patent: US 8,564,055 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a substrate, an active gate trench in the substrate, the active gate trench has a first top gate electrode and a first bottom source electrode, and a gate runner trench comprising a second top gate electrode and a second bottom source electrode. The second top gate electrode is narrower than the second bottom source electrode.

Claims

1. A semiconductor device, comprising:

a substrate;

an active gate trench in the substrate, comprising a first top gate electrode and a first bottom source electrode; and

a gate runner trench comprising a second top gate electrode and a second bottom source electrode;

wherein;

the second top gate electrode is narrower than the second bottom source electrode.

2. The semiconductor device of claim 1, wherein the gate runner trench is a termination trench that separates a high potential region from a low potential region.

3. The semiconductor device of claim 1, wherein the gate runner trench surrounds and interconnects a plurality of active gate trenches.

4. The semiconductor device of claim 1, wherein the gate runner trench includes a portion that serves as a gate pickup trench.

5. The semiconductor device of claim 1, wherein the second top gate electrode has a top surface that is below a top surface of the substrate.

6. The semiconductor device of claim 5, wherein the second top gate electrode further connects to a gate metal through a gate contact hole disposed directly on top of the second top gate electrode.

7. The semiconductor device of claim 1, further comprising a nitride spacer in proximity to a top portion of a side wall of the gate runner trench.

8. The semiconductor device of claim 7, wherein the second top gate electrode has a top surface below a bottom of the nitride spacer.

9. The semiconductor device of claim 7, wherein a top surface of a source region is substantially aligned to a bottom of the nitride spacer.

10. The semiconductor device of claim 1, wherein the active gate trench has an active gate trench wall that is lined with oxide having a first thickness in a top portion of the active gate trench and a second thickness in a bottom portion of the active gate trench, the second thickness being substantially greater than the first thickness.

11. The semiconductor device of claim 1, wherein the gate runner trench has a gate runner trench wall that is lined with oxide having a third thickness in an upper portion of the gate runner trench and a fourth thickness in a bottom portion of the gate runner trench, the third thickness being substantially greater than the fourth thickness.

12. The semiconductor device of claim 1, wherein the gate runner trench is wider than the active gate trench.

13. The semiconductor device of claim 1, wherein the gate runner trench has a first trench wall and a second trench wall;

the first trench wall is lined with oxide having a first thickness between the first sidewall and the second top gate electrode; and

the second trench wall is lined with oxide having a second thickness that is different from the first thickness.