Superjunction Structures for Power Devices and Methods of Manufacture

• US 20120273916A1
• Filed: 04/27/2011
• Published: 11/01/2012
• Est. Priority Date: 04/27/2011
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Rexer, Christopher L., Rinehimer, Mark L., Lee, Jaegil, Yilmaz, Hamza, Yun, Chongman, Reichl, Dwayne S., Pan, James, Ridley, Rodney S. Sr., Shenoy, Praveen Muraleedharan, Heidenreich, Harold
• Application Number:
  US13/095,652
• Publication Number:
  US 20120273916A1
• Time in Patent Office: Days
• US Class Current: 257/471
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/74 Thyristor-type devices, e.g. having four-zone regenerative action two-terminal thyristors H01L29/87
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Claims

1-162. -162. (canceled)

163. A high voltage device comprising:

one or more N-type epitaxial layers extending over a substrate;

a plurality of trenches extending into the one or more N-type epitaxial layers, the plurality of trenches being filled with P-type silicon material, the P-type silicon material in the plurality of trenches forming P-pillars, those portions of the one or more N-type epitaxial layers separating the P-pillars forming N-pillars such that the N-pillars and the P-pillars form alternating P-N-pillars;

a plurality of P-wells each formed in an upper portion of one of the P-pillars; and

an anode terminal comprising a Schottky barrier metal directly contacting a top surface of the N-pillars to form a Schottky contact therebetween, the Schottky barrier metal further directly contacting the P-wells.

164. The high voltage device of claim 163 wherein each P-well has a width greater than a width of the P-pillars.

165. The high voltage device of claim 163 wherein each P-well has a width substantially equal to a width of the P-pillars.

166. The high voltage device of claim 163 wherein each P-well includes a highly doped P+ region, the Schottky barrier metal direction contacting a top surface of the P+ regions to form ohmic contact therebetween.

167. The high voltage device of claim 163 wherein the Schottky contacts are formed in a Schottky region of the high voltage device, the high voltage device further comprising a MOSFET region configured to include a MOSFET.

168. A high voltage device comprising:

one or more N-type epitaxial layers extending over a substrate;

a plurality of trenches extending into the one or more N-type epitaxial layers, the plurality of trenches being filled with P-type silicon material, the P-type silicon material in the plurality of trenches forming P-pillars, those portions of the one or more N-type epitaxial layers separating the P-pillars forming N-pillars such that the N-pillars and the P-pillars form alternating P-N pillars;

an N-type epitaxial layer extending over the alternating P-N Pillars; and

an anode terminal comprising a Schottky barrier metal directly contacting a top surface of the N-type epitaxial layer to form a Schottky contact therebetween, the N-type epitaxial layer separating the Schottky barrier metal from the P-pillars so that the P-pillars float.

169. The high voltage device of claim 168 wherein the Schottky contact is formed in a Schottky region of the high voltage device, the high voltage device further comprising a MOSFET region configured to include a MOSFET.

170. A high voltage device comprising:

one or more N-type epitaxial layers extending over a substrate;

a plurality of trenches extending into the one or more N-type epitaxial layers, the plurality of trenches being filled with P-type silicon material, the P-type silicon material in the plurality of trenches forming P-pillars, those portions of the one or more N-type epitaxial layers separating the P-pillars forming N-pillars such that the N-pillars and the P-pillars form alternating P-N pillars;

an N-type implant region extending through an upper portion of the alternating P-N pillars; and

an anode terminal comprising a Schottky barrier metal directly contacting a top surface of the N-type implant region to form a Schottky contact therebetween, the N-type implant region separating the Schottky barrier metal from the P-pillars so that the P-pillars float.

171. The high voltage device of claim 170 wherein the Schottky contact is formed in a Schottky region of the high voltage device, the high voltage device further comprising a MOSFET region configured to include a MOSFET.