INTEGRATION OF SUPERJUNCTION MOSFET AND DIODE

• US 20120306009A1
• Filed: 06/03/2011
• Published: 12/06/2012
• Est. Priority Date: 06/03/2011
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Kim, Suku
• Application Number:
  US13/153,178
• Publication Number:
  US 20120306009A1
• Time in Patent Office: Days
• US Class Current: 257/334
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor structure comprises a semiconductor layer of a first conductivity type, trenches extending into the semiconductor layer, and a conductive layer of a second conductivity type lining sidewalls and bottom of each trench and forming PN junctions with the semiconductor layer. A first plurality of the trenches are disposed in a field effect transistor region that comprises a body region of the first conductivity type, source regions of the second conductivity type in the body region, and gate electrodes isolated from the body region and the source regions by a gate dielectric. A second plurality of the trenches are disposed in a Schottky region that comprises a conductive material contacting mesa surfaces of the semiconductor layer between adjacent ones of the second plurality of the trenches to form Schottky contacts. The conductive material also contacts the conductive layer proximate an upper portion of the second plurality of the trenches.

Claims

1. A semiconductor structure, comprising:

a semiconductor layer of a first conductivity type;

trenches extending into the semiconductor layer; and

a conductive layer of a second conductivity type lining sidewalls and bottom of each trench and forming PN junctions with the semiconductor layer, wherein a first plurality of the trenches are disposed in a field effect transistor (FET) region of the semiconductor structure, the FET region comprising;

a body region of the first conductivity type in the semiconductor layer;

source regions of the second conductivity type in the body region; and

gate electrodes isolated from the body region and the source regions by a gate dielectric;

wherein a second plurality of the trenches are disposed in a Schottky region of the semiconductor structure, the Schottky region comprising;

a conductive material contacting mesa surfaces of the semiconductor layer between adjacent ones of the second plurality of the trenches to form Schottky contacts, the conductive material also contacting the conductive layer proximate an upper portion of the second plurality of the trenches.

2. The semiconductor structure of claim 1 further comprising a dielectric material substantially filling a center portion of each trench between the conductive layer lining the sidewalls and the bottom of each trench.

3. The semiconductor structure of claim 1 wherein the first conductivity type is p-type and the second conductivity type is n-type.

4. The semiconductor structure of claim 1 wherein the first conductivity type is n-type and the second conductivity type is p-type.

5. The semiconductor structure of claim 1 wherein the semiconductor layer extends over a substrate of the second conductivity type, and the trenches extend through the semiconductor layer.

6. The semiconductor structure of claim 5 wherein the semiconductor layer comprises an epitaxial layer.

7. The semiconductor structure of claim 1 wherein one of the gate electrodes are disposed in each of the first plurality of the trenches, and the body region and the source regions abut the sidewalls of the first plurality of the trenches.

8. The semiconductor structure of claim 1 wherein the conductive material forms Schottky contacts with the conductive layer in the Schottky region.

9. The semiconductor structure of claim 1 wherein the conductive material comprises metal.

10. A semiconductor structure, comprising:

a field effect transistor (FET) region comprising;

a body region of a first conductivity type in a semiconductor region;

source regions of a second conductivity type in the body region;

gate electrodes isolated from the body region and the source regions by a gate dielectric; and

a conductive material extending over the FET region and contacting the source regions;

a Schottky region comprising;

a first plurality of trenches extending into the semiconductor region; and

a conductive layer of the second conductivity type lining sidewalls and bottom of each of the first plurality of trenches and forming PN junctions with the semiconductor region, wherein the conductive material extends over the Schottky region and contacts mesa surfaces of the semiconductor region between adjacent ones of the first plurality of trenches and contacts the conductive layer proximate an upper portion of the first plurality of trenches.

11. The semiconductor structure of claim 10 wherein the conductive material forms Schottky contacts with the mesa surfaces of the semiconductor region and with the conductive layer proximate the upper portion of the first plurality of trenches.

12. The semiconductor structure of claim 10 wherein the conductive material comprises metal.

13. The semiconductor structure of claim 10 wherein the semiconductor region comprises an epitaxial layer of the first conductivity type extending over a substrate of the second conductivity type, and the first plurality of trenches extend through the epitaxial layer.

14. The semiconductor structure of claim 10 wherein the gate electrodes are disposed over an upper surface of the semiconductor region, the gate dielectric extending between each gate electrode and the semiconductor region, and each gate electrode overlaps the body region and at least one of the source regions along the upper surface of the semiconductor region.

15. The semiconductor structure of claim 10 wherein the FET region further comprises a second plurality of trenches extending into the semiconductor region, the conductive layer lining sidewalls and bottom of each of the second plurality of trenches and forming PN junctions with the semiconductor region, and wherein one of the gate electrodes are disposed in each of the second plurality of trenches, and the body region and the source regions abut the sidewalls of the second plurality of trenches.

16. The semiconductor structure of claim 10 further comprising a dielectric material substantially filling a center portion of each of the first plurality of trenches between the conductive layer lining the sidewalls and the bottom of each of the first plurality of trenches.

17. The semiconductor structure of claim 10 wherein the first conductivity type is p-type and the second conductivity type is n-type.

18. The semiconductor structure of claim 10 wherein the first conductivity type is n-type and the second conductivity type is p-type.

19. A method of forming a semiconductor structure having a field effect transistor (FET) region and a Schottky region, the method comprising:

forming trenches extending into a semiconductor region;

forming a conductive layer lining sidewalls and bottom of each trench, the conductive layer forming PN junctions with the semiconductor region;

in the FET region, forming a body region of a first conductivity type in the semiconductor region, source regions of a second conductivity type in the body region, and forming gate electrodes isolated from the body region and the source regions by a gate dielectric; and

in the Schottky region, forming a conductive material contacting mesa surfaces of the semiconductor region between adjacent ones of the trenches to form Schottky contacts and contacting the conductive layer proximate an upper portion of the trenches.

20. The method of claim 19 wherein the conductive material forms Schottky contacts with the conductive layer in the Schottky region.

21. The method of claim 19 wherein the conductive material comprises metal.

22. The method of claim 19 wherein forming the conductive layer comprises growing an epitaxial layer along the sidewalls and the bottom of each trench.

23. The method of claim 19 wherein forming the conductive layer comprises implanting a dopant into the sidewalls and the bottom of each trench.

24. The method of claim 19 wherein the semiconductor region comprises an epitaxial layer of the first conductivity type extending over a substrate of the second conductivity type, the trenches extending through the epitaxial layer.

25. The method of claim 19 wherein the trenches are formed only in the Schottky region, and in the FET region the gate electrodes are formed over an upper surface of the semiconductor region such that the gate dielectric extends between each gate electrode and the semiconductor region and each gate electrode overlaps the body region and at least one of the source regions along the upper surface of the semiconductor region.

26. The method of claim 19 wherein one of the gate electrodes are formed in each of the trenches in the FET region, and the body region and the source regions abut the sidewalls of each of the trenches in the FET region.

27. The method of claim 19 wherein the first conductivity type is p-type and the second conductivity type is n-type.

28. The method of claim 19 wherein the first conductivity type is n-type and the second conductivity type is p-type.