Semiconductor Device and Method of Forming a Stackable Semiconductor Package with Vertically-Oriented Discrete Electrical Devices as Interconnect Structures

• US 20130037936A1
• Filed: 08/11/2011
• Published: 02/14/2013
• Est. Priority Date: 08/11/2011
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Choi, DaeSik, Park, YeongIm, Lee, HyungMin
• Granted Patent: US 9,190,297 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device has a substrate and first semiconductor die to the substrate. A plurality of vertically-oriented discrete electrical devices, such as a capacitor, inductor, resistor, diode, or transistor, is mounted over the substrate in proximity to the first semiconductor die. A first terminal of the discrete electrical devices is connected to the substrate. A plurality of bumps is formed over the substrate adjacent to the discrete electrical devices. An encapsulant is deposited over and between the first semiconductor die and substrate. A portion of the bumps and a second terminal of the discrete electrical devices is exposed from the encapsulant. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. The semiconductor devices are stackable and electrically connected through the substrate, discrete electrical devices, and bumps. A heat spreader or second semiconductor die can be disposed between the stacked semiconductor devices.

Claims

1. A method of making a semiconductor device, comprising:

providing a first substrate;

mounting a first semiconductor die to the first substrate;

mounting a plurality of vertically-oriented discrete electrical devices over the first substrate with a first terminal of the vertically-oriented discrete electrical devices connected to the first substrate;

forming a plurality of bumps over the first substrate adjacent to the vertically-oriented discrete electrical devices;

depositing an encapsulant over and between the first semiconductor die and first substrate so that a portion of the bumps and a second terminal of the vertically-oriented discrete electrical devices opposite the first terminal is exposed from the encapsulant; and

forming an interconnect structure over a surface of the first substrate opposite the first semiconductor die.

2. The method of claim 1, wherein the vertically-oriented discrete electrical devices include a capacitor, inductor, resistor, diode, or transistor.

3. The method of claim 1, further including:

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the first substrate, vertically-oriented discrete electrical devices, and bumps.

4. The method of claim 3, further including disposing a heat spreader between the stacked semiconductor devices.

5. The method of claim 3, further including disposing a second semiconductor die between the stacked semiconductor devices.

6. The method of claim 1, further including:

providing a second substrate; and

mounting the second substrate to the second terminal of the discrete electrical device prior to depositing the encapsulant.

7. A method of making a semiconductor device, comprising:

providing a first substrate;

mounting a semiconductor die to the first substrate;

mounting a discrete electrical device to the first substrate with a first terminal of the discrete electrical device connected to the first substrate;

depositing an encapsulant over and between the semiconductor die and first substrate so that a second terminal of the discrete electrical device opposite the first terminal is exposed from the encapsulant; and

forming a first interconnect structure over a surface of the first substrate opposite the semiconductor die.

8. The method of claim 7, further including forming a second interconnect structure over the first substrate adjacent to the discrete electrical device.

9. The method of claim 7, wherein a height of the discrete electrical device is less than a thickness of the semiconductor die.

10. The method of claim 7, further including disposing a conductive pillar or bump in line with the discrete electrical device to provide vertical standoff for the discrete electrical device.

11. The method of claim 7, wherein the discrete electrical device includes a capacitor, inductor, resistor, diode, or transistor.

12. The method of claim 7, further including:

providing a second substrate; and

mounting the second substrate to the second terminal of the discrete electrical device prior to depositing the encapsulant.

13. The method of claim 7, further including:

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the first substrate and discrete electrical device.

14. A method of making a semiconductor device, comprising:

providing a first substrate;

mounting a semiconductor die to the first substrate;

mounting a first terminal of a discrete electrical device over the first substrate; and

depositing an encapsulant over the semiconductor die and first substrate so that a second terminal of the discrete electrical device opposite the first terminal is exposed from the encapsulant.

15. The method of claim 14, further including forming an interconnect structure over the first substrate adjacent to the discrete electrical devices.

16. The method of claim 15, wherein the interconnect structures include bumps or conductive pillars.

17. The method of claim 14, further including forming an interconnect structure over a surface of the first substrate opposite the semiconductor die.

18. The method of claim 14, wherein the discrete electrical devices include a capacitor, inductor, resistor, diode, or transistor.

19. The method of claim 14, further including:

providing a second substrate; and

mounting the second substrate to the second terminal of the discrete electrical device prior to depositing the encapsulant.

20. The method of claim 14, further including:

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the first substrate and discrete electrical device.

21. A semiconductor device, comprising:

a substrate;

a semiconductor die mounted to the substrate;

a discrete electrical device mounted over the substrate with a first terminal of the discrete electrical device connected to the substrate;

a first interconnect structure formed over the substrate adjacent to the discrete electrical device;

an encapsulant deposited over the semiconductor die and substrate so that a second terminal of the discrete electrical device is exposed from the encapsulant; and

a second interconnect structure formed over a surface of the substrate opposite the semiconductor die.

22. The semiconductor device of claim 21, wherein the first interconnect structure includes bumps or conductive pillars.

23. The semiconductor device of claim 21, wherein a height of the discrete electrical device is less than a thickness of the semiconductor die.

24. The semiconductor device of claim 21, wherein the discrete electrical devices include a capacitor, inductor, resistor, diode, or transistor.

25. The semiconductor device of claim 21, further including a plurality of stacked semiconductor devices electrically connected through the substrate and discrete electrical device.