Semiconductor device and method of forming a stackable semiconductor package with vertically-oriented discrete electrical devices as interconnect structures

• US 9,190,297 B2
• Filed: 08/11/2011
• Issued: 11/17/2015
• Est. Priority Date: 08/11/2011
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac Limited
• Inventors: Choi, DaeSik, Park, YeongIm, Lee, HyungMin
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US13/208,027
• Publication Number:
  US 20130037936A1
• Time in Patent Office: 1,559 Days
• Field of Search: 257/737, 257/E21.502, 257/E21.499, 257/E23.068, 438/126, 438/107
• US Class Current: 1/1
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1094 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device has a substrate and first semiconductor die to the substrate. A plurality of vertically-oriented discrete electrical devices, such as a capacitor, inductor, resistor, diode, or transistor, is mounted over the substrate in proximity to the first semiconductor die. A first terminal of the discrete electrical devices is connected to the substrate. A plurality of bumps is formed over the substrate adjacent to the discrete electrical devices. An encapsulant is deposited over and between the first semiconductor die and substrate. A portion of the bumps and a second terminal of the discrete electrical devices is exposed from the encapsulant. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. The semiconductor devices are stackable and electrically connected through the substrate, discrete electrical devices, and bumps. A heat spreader or second semiconductor die can be disposed between the stacked semiconductor devices.

Claims

1. A method of making a semiconductor device, comprising:

providing a first substrate;

disposing a first semiconductor die over the first substrate;

disposing a plurality of vertically-oriented discrete electrical devices over the first substrate with a first terminal of the vertically-oriented discrete electrical devices connected to the first substrate;

forming a plurality of bumps over the first substrate around a perimeter of the first semiconductor die and adjacent to the vertically-oriented discrete electrical devices;

depositing an encapsulant between the first semiconductor die and first substrate and around the first semiconductor die with a portion of the bumps and a second terminal of the vertically-oriented discrete electrical devices opposite the first terminal extending from the encapsulant; and

forming an interconnect structure over a surface of the first substrate opposite the first semiconductor die.

2. The method of claim 1, wherein the vertically-oriented discrete electrical devices include a capacitor, inductor, resistor, diode, or transistor.

3. The method of claim 1, further including:

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the first substrate, vertically-oriented discrete electrical devices, and bumps.

4. The method of claim 3, further including disposing a heat spreader between the stacked semiconductor devices.

5. The method of claim 3, further including disposing a second semiconductor die between the stacked semiconductor devices.

6. A method of making a semiconductor device, comprising:

providing a first substrate;

mounting a first semiconductor die to the first substrate;

mounting a plurality of vertically-oriented discrete electrical devices over the first substrate with a first terminal of the vertically-oriented discrete electrical devices connected to the first substrate;

forming a plurality of bumps over the first substrate adjacent to the vertically-oriented discrete electrical devices;

depositing an encapsulant over and between the first semiconductor die and first substrate with a portion of the bumps and a second terminal of the vertically-oriented discrete electrical devices opposite the first terminal extending from the encapsulant;

providing a second substrate;

mounting the second substrate to the second terminal of the vertically-oriented discrete electrical devices prior to depositing the encapsulant; and

forming an interconnect structure over a surface of the first substrate opposite the first semiconductor die.

7. The method of claim 6, wherein the vertically-oriented discrete electrical devices include a capacitor, inductor, resistor, diode, or transistor.

8. The method of claim 6, further including:

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the first substrate, vertically-oriented discrete electrical devices, and bumps.

9. The method of claim 6, wherein a height of the vertically-oriented discrete electrical devices is greater than a thickness of the semiconductor die.

10. A method of making a semiconductor device, comprising:

providing a first substrate;

disposing a semiconductor die over the first substrate;

disposing a discrete electrical device over the first substrate with a first terminal of the discrete electrical device connected to the first substrate and a second terminal of the discrete electrical device vertically aligned with the first terminal;

disposing a first interconnect structure over the discrete electrical device; and

disposing a second substrate over the first interconnect structure and electrically connected through the first interconnect structure and discrete electrical device to the first substrate.

11. The method of claim 10, further including forming a second interconnect structure over the first substrate adjacent to the discrete electrical device.

12. The method of claim 10, wherein a height of the discrete electrical device is less than a thickness of the semiconductor die.

13. The method of claim 10, further including disposing a conductive pillar or bump in line with the discrete electrical device to provide vertical standoff for the discrete electrical device.

14. The method of claim 10, wherein the discrete electrical device includes a capacitor, inductor, resistor, diode, or transistor.

15. The method of claim 10, further including:

depositing an encapsulant over and between the semiconductor die and first substrate with the second terminal of the discrete electrical device extending from the encapsulant; and

disposing the second substrate over the second terminal of the discrete electrical device prior to depositing the encapsulant.

16. The method of claim 10, further including:

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the first substrate and discrete electrical device.

17. A method of making a semiconductor device, comprising:

providing a first substrate;

disposing a semiconductor die over the first substrate;

forming a first interconnect structure over the first substrate; and

disposing a discrete capacitive device over the first interconnect structure as a second interconnect structure, the discrete capacitive device including a first terminal and a second terminal vertically aligned with the first terminal of the discrete capacitive device to provide an electrical interconnect extending from the first substrate through the first interconnect structure and discrete capacitive device.

18. The method of claim 17, further including forming as third interconnect structure over the first substrate adjacent to the discrete capacitive device.

19. The method of claim 18, wherein the third interconnect structure includes bumps or conductive pillars.

20. The method of claim 17, further including forming a third interconnect structure over a surface of the first substrate opposite the semiconductor die.

21. The method of claim 17, further including:

providing a second substrate; and

disposing the second substrate over the discrete capacitive device.

22. The method of claim 17, further including:

stacking a plurality of semiconductor devices; and

electrically connecting the stacked semiconductor devices through the first substrate and discrete capacitive device.

23. A semiconductor device, comprising:

a substrate;

a semiconductor die disposed over the substrate;

an encapsulant formed over the substrate and around the semiconductor die including a top surface of the encapsulant below a surface of the semiconductor die; and

a discrete capacitive device disposed over the substrate with a first terminal of the discrete capacitive device connected to the substrate and a second terminal of the discrete capacitive device opposite the first terminal, and vertically aligned with the first terminal.

24. The semiconductor device of claim 23, further including an interconnect structure formed adjacent to the discrete capacitive device.

25. The semiconductor device of claim 23, wherein a height of the discrete capacitive device is less than a thickness of the semiconductor die.

26. The semiconductor device of claim 23, further including a plurality of stacked semiconductor devices electrically connected through the substrate and discrete capacitive device.

27. A semiconductor device, comprising:

a first substrate;

a semiconductor die disposed over a surface of the first substrate;

a capacitor disposed over the surface of the first substrate as a first interconnect structure coupled to the first substrate, the capacitor including a first terminal and a second terminal vertically aligned with the first terminal of the capacitor; and

an interconnect structure disposed over the surface of the first substrate, including a height of the interconnect structure greater than a height of the capacitor.

28. The semiconductor device of claim 27, wherein the capacitor provides z-direction vertical interconnect for the first substrate.

29. The semiconductor device of claim 27, further including a second substrate disposed over the capacitor opposite the first substrate.

30. The semiconductor device of claim 27, wherein the interconnect structure further includes a bump.

31. The semiconductor device of claim 27, further including a plurality of stacked semiconductor devices electrically connected through the capacitor.

32. A semiconductor device, comprising:

a first substrate;

a semiconductor die disposed over the first substrate;

a bump formed between the first substrate and semiconductor die; and

a discrete capacitive device disposed over the first substrate with the discrete capacitive device configured for electrically connecting the first substrate to an additional semiconductor device.

33. The semiconductor device of claim 32, further including a semiconductor package stacked over the discrete capacitive device with the first substrate electrically coupled to the semiconductor package through the discrete capacitive device.

34. The semiconductor device of claim 32, further including an encapsulant disposed over the semiconductor die, first substrate, and discrete capacitive device with a portion of the discrete capacitive device extending from the encapsulant opposite the first substrate.

35. The semiconductor device of claim 32, further including a bump disposed over the first substrate within a perimeter of the semiconductor die.

36. The semiconductor device of claim 32, further including a second substrate disposed over the discrete capacitive device opposite the first substrate.