BRANCH CIRCUIT DETERMINATION WITH SYNCHRONOUS CORRELATION

• US 20130054999A1
• Filed: 04/30/2012
• Published: 02/28/2013
• Est. Priority Date: 08/25/2011
• Status: Active Grant

• Current Assignee: Alexandre Peixoto Ferreira, Juan Carlos Rubio, Malcolm Scott Allen-Ware, Thomas Walter Jr. Keller, Wael R. El-Essawy
• Original Assignee: Malcolm Scott Allen-Ware, Thomas Walter Jr. Keller
• Inventors: ALLEN-WARE, MALCOLM SCOTT, El-Essawy, Wael R., Ferreira, Alexandre Peixoto, Keller, Thomas Walter Jr., Rubio, Juan Carlos
• Granted Patent: US 8,850,240 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for relating a data processing system with a power branch circuit is provided in the illustrative embodiments. A second signal is combined with a power signal to form a combination signal, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal. The second signal is synchronized with the modulating signal in the power signal. A determination is made whether an amplitude of a frequency of the second signal is increasing in the combined signal over a period. Responsive to the determining being affirmative, the data processing system is related with the power branch circuit.

Claims

1. A computer implemented method for relating a data processing system with a power branch circuit, the method comprising:

combining, to form a combination signal, a second signal with a power signal, the power signal including a first power usage by the data processing system and a second power usage by a modulating signal;

synchronizing the second signal with the modulating signal in the power signal;

determining whether an amplitude of a frequency of the second signal is increasing in the combined signal over a period; and

relating, responsive to the determining being affirmative, the data processing system with the power branch circuit.

2. The computer implemented method of claim 1, further comprising:

determining whether the amplitude of the frequency of the second signal exceeds a threshold, and wherein the relating is further responsive to the amplitude exceeding the threshold.

3. The computer implemented method of claim 1, further comprising:

integrating the combination signal over the period; and

sampling the combination signal at a point in time in the period to determine the amplitude.

4. The computer implemented method of claim 1, wherein the synchronizing further includes using a third signal for ensuring that the modulating signal and the second signal are in-phase with each other.

5. The computer implemented method of claim 1, wherein the synchronizing further comprises:

changing a phase of the second signal from a first phase to a second phase;

determining whether the second phase of the second signal causes the synchronizing; and

repeating the changing and the determining for a third phase of the second signal responsive to the second phase of the second signal not causing the synchronizing.

6. The computer implemented method of claim 1, wherein the synchronizing further comprises:

setting the phase of the second signal to all possible phases of the modulating signal in parallel; and

determining whether any phase of the second signal causes the synchronizing.

7. The computer implemented method of claim 1, wherein the modulating signal is a low power and low frequency load applied to the data processing system using a signal generator device.

8. The computer implemented method of claim 1, wherein the signal generator device is coupled with the data processing system using a direct current powered port on the data processing system.

9. The computer implemented method of claim 1, wherein the signal generator device is coupled with the data processing system using an alternating current powered port on the data processing system.

10. The computer implemented method of claim 1, wherein the combining is a multiplication of the second signal with the power signal.