SEMICONDUCTOR APPARATUS

• US 20130092936A1
• Filed: 12/30/2011
• Published: 04/18/2013
• Est. Priority Date: 10/18/2011
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: YANG, Hyung Gyun, LEE, Hyung Dong, KWON, Yong Kee, MOON, Young Suk, KIM, Sung Wook
• Granted Patent: US 8,618,541 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/065 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor apparatus includes first and second vias, a first circuit unit, a second circuit unit and a third circuit unit. The first and second vias electrically connect a first chip and a second chip with each other. The first circuit unit is disposed in the first chip, receives test data, and is connected with the first via. The second circuit unit is disposed in the first chip, and is connected with the second via and the first circuit unit. The third circuit unit is disposed in the second chip, and is connected with the first via. The first circuit unit outputs an output signal thereof to one of the first via and the second circuit unit in response to a first control signal.

Claims

1. A semiconductor apparatus comprising:

first and second vias electrically connecting a first chip and a second chip with each other;

a first circuit unit disposed in the first chip, configured to receive test data, and connected with the first via;

a second circuit unit disposed in the first chip, and connected with the second via and the first circuit unit;

a third circuit unit disposed in the second chip, and connected with the first via,

wherein the first circuit unit outputs an output signal thereof to one of the first via and the second circuit unit in response to a first control signal.

2. The semiconductor apparatus according to claim 1, wherein the second circuit unit outputs an output signal thereof which is generated by receiving the output signal of the first circuit unit, to the second via in response to the first control signal.

3. The semiconductor apparatus according to claim 2, wherein the second circuit unit receives the test data instead of the output signal of the first circuit unit in response to a second control signal and generates an output signal thereof.

4. The semiconductor apparatus according to claim 3, wherein the third circuit unit receives the output signal of the first circuit unit through the first via in response to the second control signal and generates an output signal thereof.

5. The semiconductor apparatus according to claim 1, further comprising:

a fourth circuit unit disposed in the second chip, and connected with the second via and the third circuit unit,

wherein the third circuit unit outputs an output signal thereof to one of the fourth circuit unit and a third via which connects the second chip with another chip stacked over the second chip, in response to the first control signal.

6. The semiconductor apparatus according to claim 5, wherein the fourth circuit unit receives one of the output signal of the second circuit unit, which is transmitted through the second via, and the output signal of the third circuit unit in response to the second control signal, and generates an output signal thereof.

7. The semiconductor apparatus according to claim 6, wherein the fourth circuit unit outputs the output signal thereof to a fourth via which connects the second chip with the another chip, in response to the first control signal.

8. The semiconductor apparatus according to claim 1, further comprising:

a fifth via electrically connecting the first and second chips with each other and configured to transmit the test data,

wherein the third circuit unit receives the test data through the fifth via in response to a third control signal.

9. A semiconductor apparatus comprising:

a scan circuit block including

a receiving section configured to generate an output signal from one of an output signal of another circuit unit which is disposed in a first chip and an output signal of a circuit unit which is disposed in a second chip, in response to a second control signal; and

an output section configured to output the output signal of the receiving section to one of still another circuit unit which is disposed in the first chip and a circuit unit which is disposed in a third chip, in response to a first control signal,

wherein the scan circuit block is disposed in the first chip.

10. The semiconductor apparatus according to claim 9, wherein the receiving section receives test data instead of the output signals of the another circuit unit which is disposed in the first chip and of the circuit unit which is disposed in the second chip, in response to a third control signal.

11. The semiconductor apparatus according to claim 10, wherein the scan circuit block further comprises:

a normal operating section configured to transmit input of the test data to a core circuit in response to a test control signal which divides a test operation and a normal operation of the semiconductor apparatus.

12. The semiconductor apparatus according to claim 11, wherein the scan circuit block further comprises:

a test control section configured to communicate with an external controller and provide the first to third control signals, the test data and the test control signal.

13. The semiconductor apparatus according to claim 12, wherein the scan circuit block further comprises:

a test output section configured to output the output signal of the receiving section to the test control section in response to an output enable signal.

14. The semiconductor apparatus according to claim 9, wherein the scan circuit block is electrically connected with the circuit unit which is disposed in the second chip, through a via, and the output signal of the circuit unit disposed in the second chip, which is received by the scan circuit block, has information as to whether a fail has occurred in the via.

15. The semiconductor apparatus according to claim 9, wherein the scan circuit block is electrically connected with the circuit unit which is disposed in the third chip, through a via, and an output of the scan circuit block, which is received by the circuit unit disposed in the third chip, has information as to whether a fail has occurred in the via.

16. A semiconductor apparatus comprising:

a first via electrically connecting a first chip and a second chip;

a first circuit unit disposed in the first chip and connected with the first via;

a second circuit unit disposed in the first chip; and

wherein the first circuit unit outputs an output signal to one of the first via and the second circuit unit in response to a first control signal.

17. The semiconductor apparatus according to claim 16, wherein the second circuit unit outputs an output signal in response to receiving the output signal of the first circuit unit, where the second circuit unit outputs the output signal to a second via that is connected to the second circuit unit and which electrically connects the first and the second chip.

18. The semiconductor apparatus according to claim 17, wherein the second circuit unit receives test data instead of the output signal of the first circuit unit, where the test data is sent in response to a second control signal.

19. The semiconductor apparatus according to claim 18, further comprising a third circuit unit disposed in the second chip, and connected with the first via, wherein the third circuit unit receives the output signal of the first circuit unit through the first via in response to the second control signal and generates an output signal.

20. The semiconductor apparatus according to claim 19, further comprising:

a fourth circuit unit disposed in the second chip, and connected with the second via and the third circuit unit,

wherein the third circuit unit outputs an output signal thereof to one of the fourth circuit unit and a third via which connects the second chip with another chip stacked over the second chip, in response to the first control signal.