NONVOLATILE MEMORY DEVICE AND DRIVING METHOD THEREOF

• US 20130114345A1
• Filed: 10/18/2012
• Published: 05/09/2013
• Est. Priority Date: 11/08/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Changhyun
• Granted Patent: US 9,147,471 B2
• Time in Patent Office: Days
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors.

Claims

1. A nonvolatile memory device, comprising:

a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the plurality of serially-connected selection transistors; and

control logic configured to perform a program operation for setting a threshold voltage of at least one of the plurality of serially-connected selection transistors.

2. The nonvolatile memory device of claim 1, wherein

the plurality of serially-connected selection transistors includes a to-be-programmed selection transistor at the one end of the plurality of serially-connected selection transistors, and

the control logic is configured to program the to-be-programmed selection transistor during the program operation to convert the to-be-programmed selection transistor into a programmed selection transistor.

3. The nonvolatile memory device of claim 2, wherein

the control logic is configured to verify the programmed selection transistor using a verification voltage after execution of the program operation, and

the verification voltage corresponds to the threshold voltage set by the control logic.

4. The nonvolatile memory device of claim 2, wherein the control logic is configured to verify the plurality of serially-connected selection transistors using a verification voltage corresponding to the threshold voltage after execution of the program operation.

5. The nonvolatile memory device of claim 1, wherein the control logic is configured to program one of the plurality of serially-connected selection transistor that is adjacent to a bit line at the program operation.

6. The nonvolatile memory device of claim 1, wherein the serially-connected selection transistors include:

a first string selection transistor connected to a bit line and programmed to have a first threshold voltage; and

a second string selection transistor connected between the first string selection transistor and the one end of the plurality of serially-connected selection transistors,

the second string selection transistor being programmed to have a second threshold voltage.

7. The nonvolatile memory device of claim 1, wherein at least two strings of the plurality of strings are connected to one bit line.

8. The nonvolatile memory device of claim 7, wherein

at least one of the serially-connected selection transistors includes a depletion type transistor or an enhancement type transistor connected to the bit line to select one of the at least two strings connected with the bit line,

wherein the depletion type transistor or the enhancement type transistor is formed by an ion implantation manner.

9. The nonvolatile memory device of claim 7, further comprising:

a substrate,

wherein each of the plurality of strings includes the plurality of selection transistors and the memory cells stacked on the substrate in a direction perpendicular to a substrate.

10. The nonvolatile memory device of claim 7, wherein the plurality of serially-connected selection transistors include:

a first string selection transistor connected to a bit line and formed by an ion implantation manner; and

a second string selection transistor connected to the first string selection transistor, a structure of the second string selection transistor is the same as a structure of each of the plurality of memory cells, and the second string selection transistor is configured to be programmed by the control logic.

11. The nonvolatile memory device of claim 7, wherein each of the at least two strings of the plurality of strings comprises:

a first string having a first enhancement type selection transistor connected to the bit line and a first depletion type selection transistor connected to the first enhancement type selection transistor; and

a second string having a second depletion type selection transistor connected to the bit line and a second enhancement type selection transistor connected to the second depletion type selection transistor,

wherein each of the first and second enhancement type selection transistors and the first and second depletion type selection transistors includes at least two selection transistors having a structure that is the same as a structure of each of the plurality of memory cells, at least one of the at least two selection transistors is configured to be programmed by the control logic.

12. The nonvolatile memory device of claim 11, wherein the control logic is configured to operate so when one of the memory cells is programmed, a first selection voltage provided to at least one unprogrammed selection transistor is different from a second selection voltage provided to a programmed selection transistor, the at least one unprogrammed selection transistor being adjacent to the programmed selection transistor.

13. The nonvolatile memory device of claim 11, wherein the control logic is configured to operate so when one of the memory cells is read, a first read pass voltage provided to at least one unprogrammed selection transistor is equal to a second read pass voltage provided to the remaining memory cells excepting the memory cell to be read, the at least one unprogrammed selection transistor being adjacent to the programmed selection transistor.

14. A nonvolatile memory device, comprising:

a plurality of memory cells connected in series;

a first selection transistor connected to one end of the memory cells and programmed to have a first threshold voltage;

a second selection transistor connected to the first selection transistor and programmed to have a second threshold voltage; and

a third selection transistor connected to the second selection transistor and programmed to have a third threshold voltage,

wherein the first threshold voltage is higher than the second and third threshold voltages.

15. The nonvolatile memory device of claim 14, wherein the first to third selection transistors are verified using a first verification voltage having the first threshold voltage after the first selection transistor is programmed, the first to third selection transistors are verified using a second verification voltage having the second threshold voltage after the second selection transistor is programmed, and the first to third selection transistors are verified using a third verification voltage having the third threshold voltage after the third selection transistor is programmed.

16. A nonvolatile memory device comprising:

a plurality of bit lines;

a common source line;

a plurality of strings between the common source line and the plurality of bit lines, each of the plurality of strings including,

a plurality of selection transistors,

the plurality of selection transistor including a ground selection transistor connected to the common source line and at least one string selection transistor connected to one of the plurality of bit lines, and

a plurality of memory cells serially-connected between the ground selection transistor and the at least one string selection transistor; and

a control logic connected to the plurality of strings,

the control logic being configured to perform a program operation for setting a threshold voltage of at least one of the plurality of selection transistors.

17. The nonvolatile memory device of claim 16, wherein

the at least one string selection transistor of the plurality of selection transistors in each of the plurality of strings includes,

a first string selection transistor connected to one of the plurality of bit lines, and

a second string selection transistor connected between the first string selection transistor and the plurality of memory cells, and

the control logic is configured to set a threshold voltage of the first string selection transistor or the second string selection transistor of a selected string among the plurality of strings during the program voltage.

18. The nonvolatile memory device of claim 16, wherein at least two strings of the plurality of string are connected to a common bit line among the plurality of bit lines.

19. The nonvolatile memory device of claim 16, wherein

two strings of the plurality of strings are connected to the common bit line,

the two strings each include 1 to i string selection transistors that are serially-connected between the plurality of memory cells and the common bit line,

i is an integer greater than or equal to 4,

the 1^st string selection transistor in one of the two strings is an enhancement type,

the 2^nd to i^th string selection transistors in the one of the two strings are a depletion type,

the 1^st string selection transistor in an other of the two strings is the depletion type,

the 2^nd to i^th string selection transistors in the other of the two strings are the enhancement type, and

the control logic is configured to set a threshold voltage of one of the 2^nd to i^th string selection transistors in a selected one of the two strings during the program operation.

20. The nonvolatile memory device of claim 16, wherein

two strings of the plurality of strings are connected to the common bit line,

the two strings each include 1 to i string selection transistors that are serially-connected between the plurality of memory cells and the common bit line,

i is an integer greater than or equal to 5,

the 1^st to j^th string selection transistors in one of the two strings are an enhancement type,

j being an integer between 1 and i,

the j+1^th to i^th string selection transistors in the one of the two strings are a depletion type,

the 1^st to j^th string selection transistors in an other of the two strings are the depletion type,

the j+1^th to i^th string selection transistors in the other of the two strings are the enhancement type, and

the control logic is configured to set a threshold voltage of one of the 1^st to i^th string selection transistors in a selected one of the two strings during the program operation.