Nonvolatile memory device and driving method thereof
First Claim
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1. A nonvolatile memory device, comprising:
- a plurality of strings, each one of the plurality of strings including a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the plurality of serially-connected selection transistors, the plurality of memory cells being stacked vertically on top of each other, the serially-connected selection transistors including,a first string selection transistor connected to a bit line and programmed to have a first threshold voltage, anda second string selection transistor connected between the first string selection transistor and the one end of the plurality of serially-connected selection transistors, the second string selection transistor being programmed to have a second threshold voltage; and
a control logic configured to perform a program operation for setting a threshold voltage of at least one of the plurality of serially-connected selection transistors.
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Abstract
According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors.
46 Citations
14 Claims
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1. A nonvolatile memory device, comprising:
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a plurality of strings, each one of the plurality of strings including a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the plurality of serially-connected selection transistors, the plurality of memory cells being stacked vertically on top of each other, the serially-connected selection transistors including, a first string selection transistor connected to a bit line and programmed to have a first threshold voltage, and a second string selection transistor connected between the first string selection transistor and the one end of the plurality of serially-connected selection transistors, the second string selection transistor being programmed to have a second threshold voltage; and a control logic configured to perform a program operation for setting a threshold voltage of at least one of the plurality of serially-connected selection transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A nonvolatile memory device, comprising:
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a plurality of memory cells connected in series; a first selection transistor connected to one end of the memory cells and programmed to have a first threshold voltage; a second selection transistor connected to the first selection transistor and programmed to have a second threshold voltage; and a third selection transistor connected to the second selection transistor and programmed to have a third threshold voltage, wherein the first threshold voltage is higher than the second and third threshold voltages. - View Dependent Claims (11)
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12. A nonvolatile memory device comprising:
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a plurality of bit lines; a common source line; a plurality of strings between the common source line and the plurality of bit lines, each of the plurality of strings including, a plurality of selection transistors, the plurality of selection transistors including a ground selection transistor connected to the common source line and at least one string selection transistor connected to one of the plurality of bit lines, and a plurality of memory cells serially-connected between the ground selection transistor and the at least one string selection transistor, the plurality of memory cells being vertically stacked on top of each other between the ground selection transistor and the at least one string selection transistor; and a control logic connected to the plurality of strings, the control logic being configured to perform a program operation for setting a threshold voltage of at least one of the plurality of selection transistors, wherein two strings of the plurality of strings are connected to a common bit line among the plurality of bit lines, the two strings each include 1 to i string selection transistors that are serially-connected between the plurality of memory cells and the common bit line, i is an integer greater than or equal to 4, the 1st string selection transistor in one of the two strings is an enhancement type, the 2nd to ith string selection transistors in the one of the two strings are a depletion type, the 1st string selection transistor in an other of the two strings is the depletion type, the 2nd to ith string selection transistors in the other of the two strings are the enhancement type, and the control logic is configured to set a threshold voltage of one of the 2nd to ith string selection transistors in a selected one of the two strings during the program operation. - View Dependent Claims (13, 14)
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Specification