TFT-LCD ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

• US 20130122622A1
• Filed: 01/09/2013
• Published: 05/16/2013
• Est. Priority Date: 02/27/2009
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: LIU, Xiang, RIM, Seung Moo, XIE, Zhenyu, CHEN, XU
• Granted Patent: US 8,917,365 B2
• Time in Patent Office: Days
• US Class Current: 438/30
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence

Abstract

A thin film transistor liquid crystal display (TFT-LCD) array substrate comprising a gate line and a data line formed on a base substrate. The gate line and the data line intersect with each other to define a pixel region, in which a pixel electrode and a thin film transistor (TFT) are formed, and a first insulating layer and a second insulating layer are interposed between the gate line and the data line, and the pixel electrode is disposed between the first insulating layer and the second insulating layer. A method of manufacturing a TFT-LCD is also disclosed.

Claims

1. A method of producing a thin film transistor liquid crystal display (TFT-LCD) array substrate, comprising:

depositing a gate metal thin film on a base substrate and patterning the gate metal film to form a gate line and a gate electrode;

sequentially depositing a first insulating layer and a transparent conductive thin film on the base substrate and patterning the transparent conductive thin film to form a pixel electrode;

sequentially depositing a second insulating layer, a semiconductor thin film and a doped semiconductor thin film on the base substrate and patterning the second insulating layer, the semiconductor thin film and the doped semiconductor thin film to form an active layer island and an insulating layer through hole in the second insulating layer, wherein the insulating layer through hole is located over the pixel electrode; and

depositing a source/drain metal thin film on the base substrate and patterning the source/drain metal thin film to form a data line, a source electrode, a drain electrode and a TFT channel region, wherein the drain electrode is connected with the pixel electrode via the insulating layer through hole, and the doped semiconductor layer in the TFT channel region is completely etched to expose the underlying semiconductor thin film.

2. The method of producing a TFT-LCD array substrate according to claim 1, wherein the forming of the active layer island and the insulating layer through hole comprises:

sequentially depositing the second insulating layer, the semiconductor layer and the doped semiconductor layer by plasma enhanced chemical vapor deposition (PECVD) method;

coating a layer of photoresist on the doped semiconductor layer;

exposing the photoresist by using a half tone or gray tone mask so as to render the photoresist comprise a photoresist-fully-retained region corresponding to a region where the active layer island is to be formed, a photoresist-fully-removed region corresponding to a region where the insulating layer through hole pattern is to be formed, and a photoresist-partially-retained region corresponding to a region other than the above regions, wherein, after a developing process on the photoresist being exposed, a thickness of the photoresist in the photoresist-fully-retained region is unchanged, the photoresist in the photoresist-fully-removed region is removed, and a thickness of the photoresist in the photoresist-partially-retained region is reduced;

etching away, by a first etching process, the doped semiconductor layer, the semiconductor layer and the second insulating layer in the photoresist-fully-removed region to form the insulating layer through hole, from which the pixel electrode is exposed;

removing, by using an ashing process, the photoresist in the photoresist-partially-retained region so as to expose the doped semiconductor layer;

etching away, by a second etching process, the doped semiconductor layer and the semiconductor layer in the photoresist-partially-retained region so as to form the active layer island; and

removing the remaining photoresist.

3. The method of producing a TFT-LCD array substrate according to claim 1, wherein the forming of the data line, the source electrode, the drain electrode and the TFT channel region comprises:

depositing the source/drain metal layer by using a magnetron sputtering or thermal evaporation method; and

patterning the source/drain metal layer by using a normal mask so as to form the data line, the source electrode, the drain electrode and the TFT channel region,

wherein one end of the source electrode is formed on the active layer island and the other end of the source electrode is connected with the data line;

one end of the drain electrode is formed on the active layer island and the other end of the drain electrode is connected with the pixel electrode via the insulating layer through hole; and

the doped semiconductor layer of the TFT channel region between the source electrode and the drain electrode is completely etched and a portion of the semiconductor layer is etched so that the semiconductor layer of the TFT channel region is exposed.

4. The method of producing a TFT-LCD array substrate according to claim 3, wherein an oxidation treatment is performed on the exposed semiconductor layer in the TFT channel region so that an oxide layer is formed on the surface of the semiconductor layer exposed via the doped semiconductor layer.

5. The method of producing a TFT-LCD array substrate according to claim 4, wherein the oxidation treatment has a radio frequency power of 5 KW-13 KW, an air pressure of 100 mT-500 mT, and a flow rate of oxygen of 1000 sccm-4000 sccm.

6. The method of producing a TFT-LCD array substrate according to claim 1, wherein the first insulating layer is deposited by a high rate depositing method, and the second insulating layer is deposited by a low rate depositing method.

7. The method of producing a TFT-LCD array substrate according to claim 6, wherein the high rate deposition has a radio frequency source power of 4500 W-7000 W, a flow rate of silane of 900 sccm-1600 sccm, and the low rate deposition has a radio frequency source power of 2500 W-4000 W, a flow rate of silane of 500 sccm-800 sccm.

8. The method of producing a TFT-LCD array substrate according to claim 1, wherein, when the gate line and the gate electrode are formed, a common electrode line extending in parallel to the gate line is formed and overlaps with the pixel electrode to be formed.

9. The method of producing a TFT-LCD array substrate according to claim 1, wherein the pixel electrode covers a portion of the gate line.

10. The method of producing a TFT-LCD array substrate according to claim 8, wherein the pixel electrode covers a portion of the gate line.

11. The method of producing a TFT-LCD array substrate according to claim 1, wherein an oxidation treatment is performed on the exposed semiconductor layer of the TFT channel region so that an oxide layer is formed on the surface of the semiconductor layer exposed via the doped semiconductor layer.

12. The method of producing a TFT-LCD array substrate according to claim 11, wherein the oxidation treatment has a radio frequency power of 5 KW-13 KW, an air pressure of 100 mT-500 mT, and a flow rate of oxygen of 1000 sccm-4000 sccm.