Method of manufacturing TFT-LCD array substrate

  • US 8,917,365 B2
  • Filed: 01/09/2013
  • Issued: 12/23/2014
  • Est. Priority Date: 02/27/2009
  • Status: Active Grant
First Claim
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1. A method of producing a thin film transistor liquid crystal display (TFT-LCD) array substrate, comprising:

  • depositing a gate metal thin film on a base substrate and patterning the gate metal film to form a gate line and a gate electrode;

    sequentially depositing a first insulating layer and a transparent conductive thin film on the base substrate and patterning the transparent conductive thin film to form a pixel electrode;

    sequentially depositing a second insulating layer, a semiconductor thin film and a doped semiconductor thin film on the base substrate and patterning the second insulating layer, the semiconductor thin film and the doped semiconductor thin film to form an active layer island and an insulating layer through hole in the second insulating layer, wherein the insulating layer through hole is located over the pixel electrode; and

    depositing a source/drain metal thin film on the base substrate and patterning the source/drain metal thin film to form a data line, a source electrode, a drain electrode and a TFT channel region, wherein the drain electrode is connected with the pixel electrode via the insulating layer through hole, and the doped semiconductor layer in the TFT channel region is completely etched to expose the underlying semiconductor thin film,wherein the forming of the active layer island and the insulating layer through hole comprises;

    sequentially depositing the second insulating layer, the semiconductor layer and the doped semiconductor layer by plasma enhanced chemical vapor deposition (PECVD) method;

    coating a layer of photoresist on the doped semiconductor layer;

    exposing the photoresist by using a half tone or gray tone mask so as to render the photoresist comprise a photoresist-fully-retained region corresponding to a region where the active layer island is to be formed, a photoresist-fully-removed region corresponding to a region where the insulating layer through hole pattern is to be formed, and a photoresist-partially-retained region corresponding to a region other than the above regions, wherein, after a developing process on the photoresist being exposed, a thickness of the photoresist in the photoresist-fully-retained region is unchanged, the photoresist in the photoresist-fully-removed region is removed, and a thickness of the photoresist in the photoresist-partially-retained region is reduced;

    etching away, by a first etching process, the doped semiconductor layer, the semiconductor layer and the second insulating layer in the photoresist-fully-removed region to form the insulating layer through hole, from which the pixel electrode is exposed;

    removing, by using an ashing process, the photoresist in the photoresist-partially-retained region so as to expose the doped semiconductor layer;

    etching away, by a second etching process, the doped semiconductor layer and the semiconductor layer in the photoresist-partially-retained region so as to form the active layer island; and

    removing the remaining photoresist.

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