MEMORY SYSTEM, DATA STORAGE DEVICE, MEMORY CARD, AND SSD INCLUDING WEAR LEVEL CONTROL LOGIC

• US 20130138870A1
• Filed: 09/06/2012
• Published: 05/30/2013
• Est. Priority Date: 11/30/2011
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: YOON, SANGYONG, JEONG, JAEYONG, LEE, CHULHO, KYUNG, KYEHYUN
• Application Number:
  US13/604,780
• Publication Number:
  US 20130138870A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

Disclosed is a memory system which includes a nonvolatile memory having a user area and a buffer area; and wear level control logic managing a mode change operation in which memory blocks of the user area are partially changed into the buffer area, based on wear level information of the nonvolatile memory.

Claims

1. A memory system comprising:

a nonvolatile memory (NVM) including multi-level memory cells (MLC), a first portion of the MLC being designated as a buffer area and operating in a first mode and a second portion of the MLC being designated as a user area and operating in a second mode different from the first mode; and

a memory controller configured to program data to the NVM using on-chip buffered programming, wherein the memory controller comprises wear level control logic configured to determine wear level information for the MLC and change a boundary designating the buffer area from the user area in response to the wear level information.

2. The memory system of claim 1, wherein the wear level information is determined in relation to MLC of the buffer area and includes at least one of program-erase (P/E) cycle information and erase loop count information.

3. The memory system of claim 1, wherein the wear level information is determined in relation to MLC of the user area and includes at least one of program-erase (P/E) cycle information and erase loop count information.

4. The memory system of claim 1, wherein the MLC of the buffer area are each configured according to the first mode to store M bit data, and the MLC of the user area are each configured according to the second mode to store N bit data, where M and N are natural numbers and M is less than N.

5. The memory system of claim 4, wherein the MLC of the buffer area are each configured according to the first mode to store only single bit data.

6. The memory system of claim 4, wherein the memory controller iteratively controls execution of a mode change operation that changes the boundary designating the buffer area from the user area in response to the wear level information.

7. The memory system of claim 6, wherein MLC of the buffer area as operated in the first mode have a program/erase (P/E) cycle endurance greater than the MLC of the user area as operated in the second mode.

8. The memory system of claim 6, wherein upon initialization of the memory system, the memory controller is further configured to set the boundary such that the first portion of the MLC includes a first memory blocks and the second portion of the MLC includes a second memory blocks, and by changing the boundary, at least one of the second memory blocks is re-designated as a first memory block and thereafter operates according to the first mode.

9. The memory system of claim 8, wherein upon initialization of the memory system, the memory controller is further configured to construct a mapping table that indicates the first mode for each of the first memory blocks and indicates the second mode for each of the second memory blocks, and after changing the boundary, the mapping table is updated to indicate the first mode for the least one of the second memory blocks re-designated as a first memory block.

10. The memory system of claim 9, wherein after changing the boundary the memory controller is further configured to update the mapping table to indicate a wear-out state for at least one of the first memory blocks.

11. The memory system of claim 1, wherein the NVM is flash memory.

12. A memory system comprising:

a nonvolatile memory (NVM) including multi-level memory cells (MLC), a first portion of the MLC being designated as a buffer area and operating in a first mode and a second portion of the MLC being designated as a user area and operating in a second mode different from the first mode; and

a memory controller configured to program data to the NVM using on-chip buffered programming, and comprising an error correction code circuit (ECC) that detects and corrects bit errors in data read from the NVM and provides ECC error rate information, and wear level control logic configured to determine wear level information for the MLC in relation to the ECC error rate information and change a boundary designating the buffer area from the user area in response to the ECC error rate information.

13. The memory system of claim 12, wherein the ECC error rate information is determined in relation to at least one of MLC in the buffer area and MLC of the user area.

14. The memory system of claim 12, wherein the MLC of the buffer area are each configured according to the first mode to store M bit data, and the MLC of the user area are each configured according to the second mode to store N bit data, where M and N are natural numbers and M is less than N.

15. The memory system of claim 14, wherein MLC of the buffer area as operated in the first mode have a program/erase (P/E) cycle endurance greater than the MLC of the user area as operated in the second mode.

16. A method of operating a memory system including a nonvolatile memory (NVM) of multi-level memory cells (MLC) and a memory controller, the method comprising:

upon initialization of the memory system, using the memory controller to designate a first portion of the MLC as a buffer area operating in a first mode and a second portion of the MLC as a user area operating in a second mode;

programming input data to the NVM under the control of the memory controller using on-chip buffered programming that always first programs the input data to the buffer area and then moves the input data from the buffer area to the user area; and

determining wear level information for the MLC and changing a boundary designating the buffer area from the user area in response to the wear level information.

17. The method of claim 16, wherein the wear level information is determined for the MLC in relation to least one of program-erase (P/E) cycle information, error rate information for data read from the MLC, and erase loop count information.

18. The method of claim 16, wherein the MLC of the buffer area store M bit data and the MLC of the user area store N bit data, where M and N are natural numbers and M is less than N.

19. The method of claim 16, wherein the first mode stores only a single data bit in the MLC of the buffer area and the second mode stores at least two data bits in the MLC of the user area.

20. The method of claim 19, wherein MLC of the buffer area have a program/erase (P/E) cycle endurance greater than the MLC of the user area.