OUTPUT BUFFER CIRCUIT
First Claim
1. An output buffer circuit comprising:
- first and second transistors which constitute a differential pair;
a first resistance component connected in common to the first and second transistors;
first and second resistance elements respectively connected in series to the first and second transistors as loads of the first and second transistors;
a second resistance component connected in parallel to the first resistance element and controlled by an input voltage of a gate terminal of the first transistor; and
a third resistance component connected in parallel to the second resistance element and controlled by an input voltage of a gate terminal of the second transistor.
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Abstract
There is provided an output buffer circuit which can reduce the time differences of the rise time and fall time of the output voltages of a differential output signal and, furthermore, can make the rise time and fall time match with a good precision. To the resistance elements R1, R2, PMOS transistors Tr5, Tr6 are connected in parallel. At this time, if designating the resistance components of the resistance elements R1, R2 as r1(Ω), r2(Ω), designating the resistance components of the PMOS transistors Tr5, Tr6 as rTr5(Ω) and rTr6(Ω), and designating the resistance component of the current source I1 as rI1(Ω), the conditions of (r1//rTr5)=(r2//rI1) and (r2//rTr6)=(r1//rI1) are satisfied. Due to this, the time differences between the rise time and fall time of the output voltages can be reduced and, furthermore, the rise time and fall time can be made to precisely match.
11 Citations
10 Claims
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1. An output buffer circuit comprising:
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first and second transistors which constitute a differential pair; a first resistance component connected in common to the first and second transistors; first and second resistance elements respectively connected in series to the first and second transistors as loads of the first and second transistors; a second resistance component connected in parallel to the first resistance element and controlled by an input voltage of a gate terminal of the first transistor; and a third resistance component connected in parallel to the second resistance element and controlled by an input voltage of a gate terminal of the second transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification
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- Resources
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Current AssigneeAsahi Kasei Microdevices Corporation (Asahi Kasei Corporation)
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Original AssigneeAsahi Kasei Microdevices Corporation (Asahi Kasei Corporation)
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InventorsFuchigami, Nobumitsu
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Application NumberUS13/822,425Publication NumberTime in Patent OfficeDaysField of SearchUS Class Current326/68CPC Class CodesH03K 19/018514 with at least one different...H03K 19/09432 with coupled sources or sou...
