Multi-Gate Field Effect Transistor with a Tapered Gate Profile

• US 20130193513A1
• Filed: 02/01/2012
• Published: 08/01/2013
• Est. Priority Date: 02/01/2012
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Bryant, Andres, Chang, Josephine B., Haensch, Wilfried, Leobandung, Effendi, Lin, Chung-Hsun
• Application Number:
  US13/363,651
• Publication Number:
  US 20130193513A1
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A multi-gate field effect transistor apparatus and method for making same. The apparatus includes a source terminal, a drain terminal, and a gate terminal which includes a tapered-gate profile. A method for designing a multi-gate field effect transistor includes arranging a source terminal, a drain terminal and a gate terminal with a tapered-gate profile to create a wider gate width on a bottom of a fin.

Claims

1. A multi-gate field effect transistor apparatus, comprising:

a source terminal;

a drain terminal; and

a gate terminal which includes a tapered-gate profile.

2. The multi-gate field effect transistor apparatus of claim 1, further comprising a hardmask.

3. The multi-gate field effect transistor apparatus of claim 2, wherein a top portion of a channel of the field effect transistor apparatus has additional gate field control via the hardmask.

4. The multi-gate field effect transistor apparatus of claim 2, wherein the gate terminal wraps around the hardmask.

5. The multi-gate field effect transistor apparatus of claim 2, wherein hardmask has a thickness ranging from approximately 0.5 nanometers to approximately 3 nanometers.

6. The multi-gate field effect transistor apparatus of claim 2, wherein hardmask has a thickness ranging from approximately 20 nanometers to approximately 30 nanometers.

7. The multi-gate field effect transistor apparatus of claim 1, wherein the tapered-gate profile comprises a bottom portion of the gate terminal having a width that is greater than a top portion of the gate terminal.

8. The multi-gate field effect transistor apparatus of claim 1, wherein a doping profile is flush with the tapered-gate profile.

9. The multi-gate field effect transistor apparatus of claim 1, wherein a doping profile overlaps the tapered-gate profile.

10. The multi-gate field effect transistor apparatus of claim 1, wherein the tapered-gate profile overlaps a doping profile.

11. The multi-gate field effect transistor apparatus of claim 1, wherein a bottom portion of a channel of the field effect transistor apparatus has additional drain field penetration via a doping profile.

12. The multi-gate field effect transistor apparatus of claim 1, wherein the gate terminal which includes a tapered-gate profile provides longer gate length in a bottom portion of a fin to lessen short channel effect penalty.

13. The multi-gate field effect transistor apparatus of claim 1, wherein the tapered-gate profile includes an angle of the tapered-gate ranging from approximately zero degrees to approximately 90 degrees.

14. The multi-gate field effect transistor apparatus of claim 1, wherein the apparatus is implemented on a silicon on insulator (SOI) substrate or a bulk substrate.

15-25. -25. (canceled)