Integrating a First Contact Structure in a Gate Last Process

• US 20130196496A1
• Filed: 03/11/2013
• Published: 08/01/2013
• Est. Priority Date: 08/26/2008
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Incorporated
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yeh, Chiung-Han, Wu, Ming-Yuan, Thei, Kong-Beng, Chuang, Harry, Liang, Mong-Song
• Granted Patent: US 8,669,153 B2
• Time in Patent Office: Days
• US Class Current: 438/586
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence

Abstract

A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.

Claims

1. A method comprising:

providing a substrate;

forming a transistor that includes a gate dielectric layer disposed over the substrate and a metal gate disposed over the gate dielectric layer; and

forming a dual contact structure that is coupled to a doped region of the transistor, wherein the forming the dual contact structure includes;

before forming the metal gate of the transistor, forming a first contact feature coupled to the doped region of the transistor, and

after forming the metal gate of the transistor, forming a second contact feature coupled to the first contact feature.

2. The method of claim 1 wherein the first contact feature and the second contact feature have a substantially same width.

3. The method of claim 1 wherein:

the forming the first contact feature coupled to the doped region of the transistor includes;

forming a first interlevel dielectric layer over the substrate and the transistor,

forming a first trench in the first interlevel dielectric layer, wherein the first trench exposes the doped region of the transistor, and

forming a first contact plug in the first trench, the first contact plug being coupled to the exposed doped region; and

the forming the second contact feature coupled to the first contact feature includes;

forming a second interlevel dielectric layer over the first interlevel dielectric layer and the transistor,

forming a second trench in the second interlevel dielectric layer, wherein the second trench exposes the first contact plug, and

forming a second contact plug in the second trench, the second contact plug being coupled to the exposed first contact plug.

4. The method of claim 3 wherein the forming the metal gate of the transistor includes:

performing a chemical mechanical polishing process on the first interlevel dielectric layer until a dummy gate of the transistor is exposed;

removing the dummy gate, thereby forming a trench; and

forming a work function metal layer and a filler metal layer in the trench, thereby forming the metal gate.

5. The method of claim 1 further including forming a metal interconnect layer over the dual contact structure, wherein the metal interconnect layer is coupled to the second contact feature.

6. The method of claim 1 further including forming a dummy dual contact structure when forming the dual contact structure.

7. The method of claim 6 wherein the forming the dummy dual contact structure when forming the dual contact structure includes:

forming a first dummy contact feature when forming the first contact feature; and

forming a second dummy contact feature when forming the second contact feature, wherein the second dummy contact feature is coupled to the first dummy contact feature.

8. A method comprising:

providing a substrate having a first region and a second region, wherein the second region has a pattern density that is substantially less than a pattern density of the first region;

forming a first transistor and a second transistor in the first region, wherein the first transistor and the second transistor each include a gate dielectric layer and a metal gate disposed over the gate dielectric layer; and

forming a dual contact structure in the first region between the first transistor and the second transistor, wherein the forming the dual contact structure includes;

before forming the metal gate of the first transistor and the second transistor, forming a first contact feature coupled to a doped region of one of the first transistor and the second transistor, and

after forming the metal gate of the first transistor and the second transistor, forming a second contact feature coupled to the first contact feature.

9. The method of claim 8 wherein the first contact feature and the second contact feature have a substantially same width.

10. The method of claim 8 further including forming a dummy dual contact structure in the second region, wherein the forming the dummy dual contact structure includes:

forming a first dummy contact feature; and

forming a second dummy contact feature coupled to the second contact feature.

11. The method of claim 10 further including:

forming the first dummy contact feature at the same time as forming the first contact feature; and

forming the second dummy contact feature at the same time as forming the second contact feature.