SEMICONDUCTOR DEVICE

• US 20130341615A1
• Filed: 06/10/2013
• Published: 12/26/2013
• Est. Priority Date: 07/16/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Kato, Kiyoshi, Nagatsuka, Shuhei
• Granted Patent: US 8,847,326 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (t_a/t_b)×(∈_ra/∈_rb)<0.1, where t_a represents the thickness of the gate insulating layer, t_b represents the thickness of the insulating layer, ∈_ra represents the dielectric constant of the gate insulating layer, and ∈_rb represents the dielectric constant of the insulating layer.

Claims

1. (canceled)

2. A semiconductor device comprising:

a first transistor;

an insulating layer over one of a source region and a drain region of the first transistor; and

a second transistor including;

a channel formation region over the insulating layer;

a gate insulating layer over the channel formation region; and

a gate electrode over the gate insulating layer,

wherein a top surface of a gate electrode of the first transistor is in contact with a bottom surface of one of a source electrode and a drain electrode of the second transistor,

wherein the gate insulating layer of the second transistor and the insulating layer satisfy a formula;

3. The semiconductor device according to claim 2, wherein the top surface of the gate electrode of the first transistor is exposed when the insulating layer is formed by chemical mechanical polishing.

4. The semiconductor device according to claim 2, wherein the channel formation region of the second transistor comprises an In—

Ga—

Zn—

O-based oxide semiconductor.

5. The semiconductor device according to claim 2, wherein an off-state current per 1 μ

m of a channel width of the second transistor is lower than 100 zA/μ

m at 25°

C.

6. The semiconductor device according to claim 2, wherein a memory cell comprises the first transistor and the second transistor.

7. The semiconductor device according to claim 2, wherein the gate insulating layer of the second transistor comprises oxygen in proportion than the stoichiometric proportion.

8. The semiconductor device according to claim 2,

wherein the thickness of the gate insulating layer of the second transistor t_a is smaller than or equal to 30 nm, and

wherein the thickness of the insulating layer t_b is larger than or equal to 90 nm.

9. A semiconductor device comprising:

a first transistor;

an insulating layer over one of a source region and a drain region of the first transistor; and

a second transistor including;

a channel formation region over the insulating layer;

a gate insulating layer over the channel formation region; and

a gate electrode over the gate insulating layer,

wherein a level of a top surface of a gate electrode of the first transistor is substantially the same as a level of a top surface of the insulating layer,

wherein the gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor,

wherein the gate insulating layer of the second transistor and the insulating layer satisfy a formula;

10. The semiconductor device according to claim 9, wherein the top surface of the gate electrode of the first transistor is exposed when the insulating layer is formed by chemical mechanical polishing.

11. The semiconductor device according to claim 9, wherein the channel formation region of the second transistor comprises an In—

Ga—

Zn—

O-based oxide semiconductor.

12. The semiconductor device according to claim 9, wherein an off-state current per 1 μ

m of a channel width of the second transistor is lower than 100 zA/μ

m at 25°

C.

13. The semiconductor device according to claim 9, wherein a memory cell comprises the first transistor and the second transistor.

14. The semiconductor device according to claim 9, wherein the gate insulating layer of the second transistor comprises oxygen in proportion than the stoichiometric proportion.

15. The semiconductor device according to claim 9,

wherein the thickness of the gate insulating layer of the second transistor t_a is smaller than or equal to 30 nm, and

wherein the thickness of the insulating layer t_b is larger than or equal to 90 nm.

16. A semiconductor device comprising:

a first transistor;

an insulating layer over one of a source region and a drain region of the first transistor; and

a second transistor including;

a channel formation region over the insulating layer;

a gate insulating layer over the channel formation region; and

a gate electrode over the gate insulating layer,

wherein a top surface of a gate electrode of the first transistor is in contact with a bottom surface of one of a source electrode and a drain electrode of the second transistor,

wherein a channel formation region of the first transistor comprises silicon,

wherein the channel formation region of the second transistor comprises an oxide semiconductor,

wherein the gate insulating layer of the second transistor and the insulating layer satisfy a formula;

17. The semiconductor device according to claim 16, wherein the top surface of the gate electrode of the first transistor is exposed when the insulating layer is formed by chemical mechanical polishing.

18. The semiconductor device according to claim 16, wherein the oxide semiconductor is an In—

Ga—

Zn—

O-based oxide semiconductor.

19. The semiconductor device according to claim 16, wherein an off-state current per 1 μ

m of a channel width of the second transistor is lower than 100 zA/μ

m at 25°

C.

20. The semiconductor device according to claim 16, wherein a memory cell comprises the first transistor and the second transistor.

21. The semiconductor device according to claim 16, wherein the gate insulating layer of the second transistor comprises oxygen in proportion than the stoichiometric proportion.

22. The semiconductor device according to claim 16,

wherein the thickness of the gate insulating layer of the second transistor t_a is smaller than or equal to 30 nm, and

wherein the thickness of the insulating layer t_b is larger than or equal to 90 nm.