SYSTEM AND METHOD TO ARBITRATE ACCESS TO MEMORY

• US 20140082307A1
• Filed: 09/17/2012
• Published: 03/20/2014
• Est. Priority Date: 09/17/2012
• Status: Abandoned Application

• Current Assignee: MobilEye Vision Technologies Ltd. (Intel Corporation)
• Original Assignee: Mobileye Technologies Limited (Intel Corporation)
• Inventors: Kreinin, Yosef, Arbeli, Yosi
• Application Number:
  US13/621,308
• Publication Number:
  US 20140082307A1
• Time in Patent Office: Days
• US Class Current: 711/158
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36

Abstract

Arbitrating memory access between a central processing unit CPU and a peripheral device to main memory. The memory access to and from the main memory by the CPU and memory access to and from the main memory by the peripheral device is prioritized respectively according to a CPU priority level and a peripheral device priority level. An arbitration module is provided externally to the CPU, to the peripheral device and to the memory controller. The arbitration module receives the peripheral device priority level. When the CPU priority level and the peripheral device priority level are both set at the highest available priority level, the arbitration module outputs to the memory controller a new CPU priority level less than the highest available priority level.

Claims

1. A system comprising:

a central processing unit (CPU);

a peripheral device;

a memory controller configured to control a main memory, wherein the CPU and peripheral devices operatively connect to said memory controller;

wherein access to and from the main memory by the CPU and access to and from the main memory by the peripheral device is prioritized respectively according to a CPU priority level and a peripheral device priority level;

an arbitration module operatively attached to the CPU, the peripheral device and the memory controller, wherein the arbitration module is configured to receive the peripheral device priority level and when the CPU priority level and the peripheral device priority level are both set at the highest available priority level, the arbitration module is configured to output to the memory controller a new CPU priority level less than the highest available priority level.

2. The system of claim 1, wherein the arbitration module is configured to receive the CPU priority level and when the CPU priority level and the peripheral device priority level are set at different priority levels, the arbitration module is configured to output to the memory controller, the new CPU priority level equal to the CPU priority level as received

3. The system of claim 1, wherein the CPU priority level is a predetermined constant value equal to the highest available priority level.

4. The system of claim 1, wherein said CPU priority level is settable by either said CPU or a device external to said CPU.

5. The system of claim 1, wherein the arbitration module is configured to receive the CPU priority level.

6. The system of claim 1, wherein said peripheral device priority level is settable by either said peripheral device or a device external to the peripheral device.

7. The system of claim 1, wherein the peripheral device is a video controller adapted to write streaming image data into the main memory.

8. The system of claim 7, wherein the video controller includes a write buffer for temporary storage of the image data prior to writing the image data into the main memory, whereby the video controller sets and outputs to the arbitration module the highest available priority level when the write buffer is substantially full, whereby the video controller sets and outputs to the arbitration module a priority level less than the highest available priority level when the write buffer is less than substantially full.

9. The system of claim 1, wherein the video controller includes a write buffer for temporary storage of the image data prior to writing the image data into the main memory and wherein the priority level for the peripheral device may be set at a value proportional to the fullness of the write buffer.

10. The system of claim 1, wherein the peripheral device is a video controller adapted to read streaming image data from the main memory.

11. The system of claim 10, wherein the video controller includes a read buffer for temporary storage of the image data prior to outputting the image data read from the main memory, whereby the video controller sets and outputs to the arbitration module the highest available priority level when the read buffer is substantially empty, whereby the video controller sets and outputs to the arbitration module a priority level less than the highest available priority level when the read buffer is not substantially empty.

12. The system of claim 1, wherein the peripheral device includes a read buffer for temporary storage of the image data prior to outputting the image data read from the main memory and wherein the priority level for the peripheral device is set at a value proportional to the emptiness of the read buffer.

13. A method for arbitrating memory access between a central processing unit CPU and a peripheral device to main memory, wherein the memory access to and from the main memory by the CPU and to and from the main memory by the peripheral device is prioritized according to a CPU priority level and a peripheral device priority level, the method comprising:

providing an arbitration module external to the CPU, the peripheral device and the memory controller;

receiving by the arbitration module the peripheral device priority level from the peripheral device; and

when the CPU priority level and the peripheral device priority level are both set at the highest available priority level outputting by the arbitration module to the memory controller, a new CPU priority level less than the highest available priority level.

14. The method of claim 13, further comprising:

setting the CPU priority level by either said CPU or a device external to said CPU.

15. The method of claim 13, further comprising:

setting the peripheral device priority level by the peripheral device.