High Speed Processing of Financial Information Using FPGA Devices

• US 20140089163A1
• Filed: 11/27/2013
• Published: 03/27/2014
• Est. Priority Date: 06/19/2006
• Status: Active Grant

• Current Assignee: Exegy Incorporated
• Original Assignee: Ip Reservoir, LLC
• Inventors: Parsons, Scott, Taylor, David E., Schuehler, David Vincent, Franklin, Mark A., Chamberlain, Roger D.
• Granted Patent: US 9,672,565 B2
• Time in Patent Office: Days
• US Class Current: 705/37
• CPC Class Codes: G06Q 40/00 Finance; Insurance; Tax strategies; Processing of corporate or income taxes
• CPC Class Codes: G06Q 40/04 Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange
• CPC Class Codes: G06Q 40/06 Asset management; Financial planning or analysis

Abstract

Methods and systems for processing financial market data using a reconfigurable logic device are disclosed. Various operations such as volume weighted average price (VWAP) operations can be performed on the financial market data using firmware logic deployed on the reconfigurable logic device to accelerate the speed of processing.

Claims

1. An apparatus for processing financial market data, the apparatus comprising:

a reconfigurable logic device having firmware logic deployed thereon that is configured to (1) receive a plurality of streaming financial market data messages, each streaming financial market data message being associated with a financial instrument, and (2) compute a volume weighted average price (VWAP) for at least one of the financial instruments based on the received financial market data messages that are associated with the at least one financial instrument.

2. The apparatus of claim 1 wherein the firmware logic is further configured to store the computed VWAP in a memory in association with the financial instrument to which the computed VWAP pertains.

3. The apparatus of claim 2 wherein the received financial market data messages comprise a plurality of fields, the fields comprising a price field and a trade size field, and wherein the firmware logic is further configured to compute the VWAP for a financial instrument based on the price and trade size fields of a plurality of received financial market data messages pertaining to that financial instrument.

4. The apparatus of claim 3 wherein the firmware logic comprises a calculation engine, the calculation engine deployed on the reconfigurable logic device as a firmware application module within a pipeline of a plurality of firmware application modules.

5. The apparatus of claim 4 wherein a firmware application module in the pipeline upstream from the calculation engine comprises a filter, the filter configured to receive a plurality of the financial market data messages and filter those received financial market data messages based on a plurality of criteria to determine which financial market data messages are to be processed by the downstream calculation engine.

6. The apparatus of claim 5 wherein the plurality of criteria comprise at least one member of the group consisting of trade size, trade type, and market conditions.

7. The apparatus of claim 4 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

8. The apparatus of claim 4 wherein the firmware application modules further comprise an alert generation engine within the pipeline downstream from the calculation engine, the alert generation engine configured to generate an alert for consumption by a downstream application in response to a specified condition being met.

9. The apparatus of claim 2 further comprising the memory, the memory for storing a plurality of records associated with a plurality of financial instruments, the records comprising a plurality of fields, at least a plurality of the financial instrument records including a field for storing the computed VWAP for its associated financial instrument.

10. The apparatus of claim 9 wherein the memory comprises memory external to the reconfigurable logic device.

11. The apparatus of claim 9 wherein the firmware logic comprises a plurality of firmware application modules (FAMs) arranged in a pipeline, the pipeline comprising a first FAM and a second FAM, the second FAM being downstream from the first FAM;

wherein the first FAM is configured to (1) receive a plurality of the streaming financial market data messages, each of the received streaming financial market data messages comprising (i) a symbol string for identifying the message'"'"'s associated financial instrument and (ii) financial market data that is representative of a price and a trade size for the message'"'"'s associated financial instrument, (2) map the symbol strings to a plurality of internal symbol IDs for the records corresponding to the messages'"'"' associated financial instruments, and (3) generate a plurality of output messages comprising the internal symbol IDs; and

wherein the second FAM is configured to (1) receive the internal symbol IDs and the financial market data, and (2) perform a plurality of calculation operations in response to the received internal symbol IDs and the received financial market data to compute a plurality of VWAPs for the financial instrument records corresponding to the received internal symbol IDs; and

wherein the first FAM and the second FAM are configured to operate simultaneously with respect to each other in a pipelined fashion.

12. The apparatus of claim 11 wherein the second FAM is further configured to compute the VWAPs for the financial instrument records at hardware processing speeds as financial market data and internal symbol IDs are received by the second FAM.

13. The apparatus of claim 12 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

14. The apparatus of claim 11 wherein the first FAM and the second FAM are configured to operate simultaneously with respect to each other in the pipelined fashion such that the first FAM is configured to perform its operations with regard to a financial market data message while the second FAM performs its operations with regard to another financial market data message.

15. The apparatus of claim 11 wherein the internal symbol IDs comprise a plurality of record keys for a plurality of financial instrument records corresponding to financial instruments associated with the received financial market data messages.

16. The apparatus of claim 1 wherein the firmware logic comprises a firmware socket module and a firmware application module pipeline;

wherein the firmware socket module is configured to (1) stream the streaming financial market data messages into the reconfigurable logic device from memory outside the reconfigurable logic device, and (2) provide the streaming financial market data messages to the firmware application module pipeline; and

wherein the firmware application module pipeline is configured to compute a plurality of VWAPs for a plurality of the financial instruments associated with the streaming financial market data messages that were provided to the firmware application module pipeline.

17. The apparatus of claim 16 wherein the firmware socket module is further configured to stream the streaming financial market data messages into the reconfigurable logic device from the outside memory via DMA operations.

18. The apparatus of claim 17 wherein the firmware socket module is further configured to provide both command data and the streaming financial market data messages to the firmware application module pipeline, wherein the firmware application module pipeline is further configured arrange itself in accordance with the command data to control how the firmware application module operates.

19. The apparatus of claim 18 further comprising a processor and a bus, wherein the processor and the reconfigurable logic device are in communication with the bus, wherein the processor, bus, and reconfigurable logic device are part of a ticker plant, wherein the reconfigurable logic device is further configured to access the command data and the streaming financial market data messages via the bus, and wherein the processor is further configured to generate the command data.

20. The apparatus of claim 19 wherein the processor is further configured to execute an operating system, the operating system including a user space for a user mode and a kernel space for a kernel mode, wherein the processor is further configured to (1) receive the streaming financial market data messages as traffic through a protocol stack, and (2) process the streaming financial market data messages from the protocol stack within the kernel space while in the kernel mode without requiring a transition to the user mode.

21. The apparatus of claim 20 wherein the processor is further configured to directly route the streaming financial market data messages for delivery to the reconfigurable logic device without a transition to the user mode.

22. A method for processing financial market data, the method comprising:

receiving a plurality of streaming financial market data messages, each streaming financial market data message being associated with a financial instrument; and

computing a volume weighted average price (VWAP) for at least one of the financial instruments based on the received financial market data messages that are associated with the at least one financial instrument; and

wherein the method steps are performed by firmware logic deployed on a reconfigurable logic device.

23. The method of claim 22 further comprising the firmware logic storing the computed VWAP in a memory in association with the financial instrument to which the computed VWAP pertains.

24. The method of claim 23 wherein the received financial market data messages comprise a plurality of fields, the fields comprising a price field and a trade size field, and wherein the computing step further comprises the firmware logic computing the VWAP for a financial instrument based on the price and trade size fields of a plurality of received financial market data messages pertaining to that financial instrument.

25. The method of claim 24 wherein the firmware logic comprises a calculation engine, the calculation engine deployed on the reconfigurable logic device as a firmware application module within a pipeline of a plurality of firmware application modules.

26. The method of claim 25 wherein a firmware application module in the pipeline upstream from the calculation engine comprises a filter, the filter (1) receiving a plurality of the financial market data messages, and (2) filtering those received financial market data messages based on a plurality of criteria to determine which financial market data messages are to be processed by the downstream calculation engine.

27. The method of claim 26 wherein the plurality of criteria comprise at least one member of the group consisting of trade size, trade type, and market conditions.

28. The method of claim 25 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

29. The method of claim 25 wherein the firmware application modules further comprise an alert generation engine within the pipeline downstream from the calculation engine, the alert generation engine generating an alert for consumption by a downstream application in response to a specified condition being met.

30. The method of claim 23 further comprising the memory, the memory for storing a plurality of records associated with a plurality of financial instruments, the records comprising a plurality of fields, at least a plurality of the financial instrument records including a field for storing the computed VWAP for its associated financial instrument.

31. The method of claim 30 wherein the memory comprises memory external to the reconfigurable logic device.

32. The method of claim 23 wherein the firmware logic comprises a plurality of firmware application modules (FAMs) arranged in a pipeline, the pipeline comprising a first FAM and a second FAM, the second FAM being downstream from the first FAM, the method further comprising:

the first FAM (1) receiving a plurality of the streaming financial market data messages, each of the received streaming financial market data messages comprising (i) a symbol string for identifying the message'"'"'s associated financial instrument and (ii) financial market data that is representative of a price and a trade size for the message'"'"'s associated financial instrument, (2) mapping the symbol strings to a plurality of internal symbol IDs for the records corresponding to the messages'"'"' associated financial instruments, and (3) generating a plurality of output messages comprising the internal symbol IDs; and

the second FAM (1) receiving the internal symbol IDs and the financial market data, and (2) performing a plurality of calculation operations in response to the received internal symbol IDs and the received financial market data to compute a plurality of VWAPs for the financial instrument records corresponding to the received internal symbol IDs; and

wherein the first FAM and the second FAM are operating simultaneously with respect to each other in a pipelined fashion.

33. The method of claim 32 wherein the performing step comprises the second FAM computing the VWAPs for the financial instrument records at hardware processing speeds as financial market data and internal symbol IDs are received by the second FAM.

34. The method of claim 33 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

35. The method of claim 32 wherein the first FAM and the second FAM operate simultaneously with respect to each other in the pipelined fashion such that the first FAM performs its operations with regard to a financial market data message while the second FAM performs its operations with regard to another financial market data message.

36. The method of claim 32 wherein the internal symbol IDs comprise a plurality of record keys for a plurality of financial instrument records corresponding to financial instruments associated with the received financial market data messages.

37. The method of claim 22 wherein the firmware logic comprises a firmware socket module and a firmware application module pipeline, the method further comprising:

the firmware socket module (1) streaming the streaming financial market data messages into the reconfigurable logic device from memory outside the reconfigurable logic device, and (2) providing the streaming financial market data messages to the firmware application module pipeline; and

the firmware application module pipeline computing a plurality of VWAPs for a plurality of the financial instruments associated with the streaming financial market data messages that were provided to the firmware application module pipeline.

38. The method of claim 37 wherein the streaming step comprises the firmware socket module streaming the streaming financial market data messages into the reconfigurable logic device from the outside memory via DMA operations.

39. The method of claim 38 further comprising:

the firmware socket module providing both command data and the streaming financial market data messages to the firmware application module pipeline; and

the firmware application module pipeline arranging itself in accordance with the command data to control how the firmware application module operates.

40. The method of claim 39 wherein the reconfigurable logic device is in communication with a processor via a bus, and wherein the processor, bus, and reconfigurable logic device are part of a ticker plant, the method further comprising;

the processor generating the command data; and

the reconfigurable logic device accessing the command data and the streaming financial market data messages via the bus.

41. The method of claim 40 further comprising:

the processor executing an operating system, the operating system including a user space for a user mode and a kernel space for a kernel mode;

the processor receiving the streaming financial market data messages as traffic through a protocol stack;

the processor processing the streaming financial market data messages from the protocol stack within the kernel space while in the kernel mode without requiring a transition to the user mode.

42. The method of claim 41 further comprising:

the processor directly routing the streaming financial market data messages for delivery to the reconfigurable logic device without a transition to the user mode.