High speed processing of financial information using FPGA devices

• US 9,672,565 B2
• Filed: 11/27/2013
• Issued: 06/06/2017
• Est. Priority Date: 06/19/2006
• Status: Active Grant

• Current Assignee: Exegy Incorporated
• Original Assignee: Ip Reservoir, LLC
• Inventors: Parsons, Scott, Taylor, David E., Schuehler, David Vincent, Franklin, Mark A., Chamberlain, Roger D.
• Primary Examiner(s): Borlinghaus, Jason M
• Application Number:
  US14/092,019
• Publication Number:
  US 20140089163A1
• Time in Patent Office: 1,287 Days
• Field of Search: 705 36 R
• CPC Class Codes: G06Q 40/00 Finance; Insurance; Tax strategies; Processing of corporate or income taxes
• CPC Class Codes: G06Q 40/04 Trading; Exchange, e.g. stocks, commodities, derivatives or currency exchange
• CPC Class Codes: G06Q 40/06 Asset management; Financial planning or analysis

Abstract

Methods and systems for processing financial market data using a reconfigurable logic device are disclosed. Various operations such as volume weighted average price (VWAP) operations can be performed on the financial market data using firmware logic deployed on the reconfigurable logic device to accelerate the speed of processing.

Claims

1. An apparatus for processing financial market data, the apparatus comprising:

a computer system comprising a processor and a reconfigurable logic device that are configured to cooperate with each other to process streaming financial market data relating to a plurality of financial instruments;

wherein the processor is configured to (1) execute an operating system that includes a user space for a user mode and a kernel space for a kernel mode, (2) receive a feed of streaming financial market data through a network protocol stack, wherein the streaming financial market data comprises volume and price information corresponding to a plurality of financial instruments, (3) use shared memory that is mapped into the kernel space and the user space to store financial market data within the streaming financial market data while the financial market data is being processed by the processor, and (4) facilitate DMA transfers of the stored financial market data to the reconfigurable logic device from the shared memory; and

the reconfigurable logic device having firmware logic deployed thereon that is configured to (1) receive financial market data from the shared memory via the DMA transfers, and (2) compute a volume weighted average price (VWAP) for each of a plurality of the financial instruments corresponding to the received financial market data based on volume and pricing information within the received financial market data.

2. The apparatus of claim 1 wherein the firmware logic is further configured to store the computed VWAPs in a memory in association with the financial instruments to which the computed VWAPs pertain.

3. The apparatus of claim 2 wherein the streaming financial market data comprises a plurality of fields, the fields comprising a price field and a trade size field, and wherein the firmware logic is further configured to compute the VWAPs for the financial instruments based on the price and trade size fields within the received financial market data pertaining to those financial instruments.

4. The apparatus of claim 3 wherein the firmware logic comprises a calculation engine, the calculation engine deployed on the reconfigurable logic device as a firmware application module within a pipeline of a plurality of firmware application modules.

5. The apparatus of claim 4 wherein a firmware application module in the pipeline upstream from the calculation engine comprises a filter, the filter configured to filter financial market data within the received financial market data based on a plurality of criteria to determine which financial market data is to be processed by the downstream calculation engine.

6. The apparatus of claim 5 wherein the plurality of criteria comprise at least one member of the group consisting of trade size, trade type, and market conditions.

7. The apparatus of claim 4 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

8. The apparatus of claim 4 wherein the firmware application modules further comprise an alert generation engine within the pipeline downstream from the calculation engine, the alert generation engine configured to generate an alert for consumption by a downstream application in response to a specified condition being met.

9. The apparatus of claim 2 further comprising the memory in which the computed VWAPs are stored in association with financial instruments, the memory for storing a plurality of records associated with a plurality of financial instruments, the records comprising a plurality of fields, at least a plurality of the financial instrument records including a field for storing the computed VWAP for its associated financial instrument.

10. The apparatus of claim 9 wherein the memory comprises memory external to the reconfigurable logic device.

11. The apparatus of claim 9 wherein the streaming financial market data comprises a symbol field that includes a symbol string for identifying the financial instruments associated with the volume and pricing information, and wherein the firmware logic comprises a plurality of firmware application modules (FAMs) arranged in a pipeline, the pipeline comprising a first FAM and a second FAM, the second FAM being downstream from the first FAM;

wherein the first FAM is configured to (1) map the symbol strings within the received financial market data to a plurality of internal symbol IDs for the records corresponding to the financial instruments corresponding to those symbol strings, and (2) generate a plurality of output messages comprising the internal symbol IDs; and

wherein the second FAM is configured to (1) receive the internal symbol IDs and the financial market data corresponding to the received internal symbol IDs, and (2) perform a plurality of calculation operations in response to the received internal symbol IDs and the received corresponding financial market data to compute a plurality of VWAPs for the financial instrument records corresponding to the received internal symbol IDs; and

wherein the first FAM and the second FAM are configured to operate simultaneously with respect to each other in a pipelined fashion.

12. The apparatus of claim 11 wherein the second FAM is further configured to compute the VWAPs for the financial instrument records at hardware processing speeds as financial market data and internal symbol IDs are received by the second FAM.

13. The apparatus of claim 12 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

14. The apparatus of claim 11 wherein the first FAM and the second FAM are configured to operate simultaneously with respect to each other in the pipelined fashion such that the first FAM is configured to perform its operations with regard to financial market data while the second FAM performs its operations with regard to other financial market data.

15. The apparatus of claim 11 wherein the internal symbol IDs comprise a plurality of record keys for a plurality of financial instrument records corresponding to financial instruments associated with the received financial market data.

16. The apparatus of claim 1 wherein the firmware logic comprises a firmware socket module and a firmware application module pipeline;

wherein the firmware socket module is configured to (1) stream the financial market data into the reconfigurable logic device from the shared memory via the DMA transfers, and (2) provide the streaming financial market data to the firmware application module pipeline; and

wherein the firmware application module pipeline is configured to compute a plurality of VWAPs for a plurality of the financial instruments associated with the streaming financial market data that was provided to the firmware application module pipeline.

17. The apparatus of claim 16 wherein the firmware socket module is further configured to provide both command data and the streaming financial market data to the firmware application module pipeline, wherein the firmware application module pipeline is further configured arrange itself in accordance with the command data to control how the firmware application module operates.

18. The apparatus of claim 17 further comprising a bus, wherein the processor and the reconfigurable logic device are in communication with the bus, wherein the processor, bus, and reconfigurable logic device are part of a ticker plant, wherein the reconfigurable logic device is further configured to access the command data and the streaming financial market data via the bus, and wherein the processor is further configured to generate the command data.

19. The apparatus of claim 1 wherein the processor is further configured to (1) normalize financial market data within the streaming financial market data, (2) use the shared memory to store the normalized financial market data, and (3) facilitate DMA transfers of the normalized financial market data to the reconfigurable logic device from the shared memory.

20. The apparatus of claim 19 wherein the shared memory comprises first shared memory that is mapped into the kernel space and the user space and second shared memory that is mapped into the kernel space and the user space, wherein a first driver that executes within the kernel space of the operating system while the operating system is in the kernel mode is configured to (1) maintain a kernel level interface into the network protocol stack, and (2) copy the streaming financial market data from the network protocol stack into the first shared memory without a transition to the user mode;

and

wherein user mode code that executes within the user space of the operating system is configured to (1) access financial market data from the first shared memory, (2) normalize the accessed financial market data, and (3) write the normalized financial market data to the second shared memory.

47. The apparatus of claim 20 wherein a second driver that executes within the kernel space of the operating system while the operating system is in the kernel mode is configured to facilitate the DMA transfers of the normalized financial market data from the second shared memory to the reconfigurable logic device.

48. The apparatus of claim 47 wherein the user mode code comprises a plurality of threads, each thread configured for execution to normalize a different group of the accessed financial market data independently of the other threads.

49. The apparatus of claim 2 wherein a driver that executes within the kernel space of the operating system while the operating system is in the kernel mode is configured to (1) read financial market data that includes a plurality of the computed VWAPs from the memory in which the computed VWAPs are stored, and (2) selectively route the read financial market data that includes a plurality of the computed VWAPs for delivery to a plurality of clients via a path that is wholly within the kernel space.

50. The apparatus of claim 49 wherein the driver comprises a plurality of drivers that execute within the kernel space of the operating system while the operating system is in the kernel mode.

51. The apparatus of claim 1 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

52. The apparatus of claim 1 wherein the shared memory comprises a ring buffer.

21. A method for processing financial market data using a computer system comprising a processor and a reconfigurable logic device, the method comprising:

the processor executing an operating system that includes a user space for a user mode and a kernel space for a kernel mode, wherein the executing step comprises;

the processor receiving a feed of streaming financial market data through a network protocol stack, wherein the streaming financial market data comprises volume and price information corresponding to a plurality of financial instruments;

the processor using shared memory that is mapped into the kernel space and the user space to store financial market data within the streaming financial market data while the financial market data is being processed by the processor; and

the processor facilitating DMA transfers of the stored financial market data to the reconfigurable logic device from the shared memory;

the reconfigurable logic device receiving financial market data from the shared memory via the DMA transfers, wherein the reconfigurable logic device comprises firmware logic that is deployed thereon; and

the firmware logic computing a volume weighted average price (VWAP) for each of a plurality of the financial instruments corresponding to the received financial market data based on volume and pricing information within the received financial market data.

22. The method of claim 21 further comprising the firmware logic storing the computed VWAPs in a memory in association with the financial instruments to which the computed VWAPs pertain.

23. The method of claim 22 wherein the streaming financial market data comprises a plurality of fields, the fields comprising a price field and a trade size field, and wherein the computing step further comprises the firmware logic computing the VWAPs for the financial instruments based on the price and trade size fields within the received financial market data pertaining to those financial instruments.

24. The method of claim 23 wherein the firmware logic comprises a calculation engine, the calculation engine deployed on the reconfigurable logic device as a firmware application module within a pipeline of a plurality of firmware application modules.

25. The method of claim 24 wherein a firmware application module in the pipeline upstream from the calculation engine comprises a filter, the filter (1) filtering financial market data within the received financial market data based on a plurality of criteria to determine which financial market data is to be processed by the downstream calculation engine.

26. The method of claim 25 wherein the plurality of criteria comprise at least one member of the group consisting of trade size, trade type, and market conditions.

27. The method of claim 24 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

28. The method of claim 24 wherein the firmware application modules further comprise an alert generation engine within the pipeline downstream from the calculation engine, the alert generation engine generating an alert for consumption by a downstream application in response to a specified condition being met.

29. The method of claim 22 further comprising the memory in which the computed VWAPs are stored in association with financial instruments, the memory storing a plurality of records associated with a plurality of financial instruments, the records comprising a plurality of fields, at least a plurality of the financial instrument records including a field for storing the computed VWAP for its associated financial instrument.

30. The method of claim 29 wherein the memory comprises memory external to the reconfigurable logic device.

31. The method of claim 22 wherein the streaming financial market data comprises a symbol field that includes a symbol string for identifying the financial instruments associated with the volume and pricing information, and wherein the firmware logic comprises a plurality of firmware application modules (FAMs) arranged in a pipeline, the pipeline comprising a first FAM and a second FAM, the second FAM being downstream from the first FAM, the method further comprising:

the first FAM (1) mapping the symbol strings within the received financial market data to a plurality of internal symbol IDs for the records corresponding to the financial instruments corresponding to those symbol strings, and (2) generating a plurality of output messages comprising the internal symbol IDs; and

the second FAM (1) receiving the internal symbol IDs and the financial market data corresponding to the received internal symbol IDs, and (2) performing a plurality of calculation operations in response to the received internal symbol IDs and the received corresponding financial market data to compute a plurality of VWAPs for the financial instrument records corresponding to the received internal symbol IDs; and

wherein the first FAM and the second FAM are operating simultaneously with respect to each other in a pipelined fashion.

32. The method of claim 31 wherein the performing step comprises the second FAM computing the VWAPs for the financial instrument records at hardware processing speeds as financial market data and internal symbol IDs are received by the second FAM.

33. The method of claim 32 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

34. The method of claim 31 wherein the first FAM and the second FAM operate simultaneously with respect to each other in the pipelined fashion such that the first FAM performs its operations with regard to financial market data while the second FAM performs its operations with regard to other financial market data.

35. The method of claim 31 wherein the internal symbol IDs comprise a plurality of record keys for a plurality of financial instrument records corresponding to financial instruments associated with the received financial market data.

36. The method of claim 21 wherein the firmware logic comprises a firmware socket module and a firmware application module pipeline, the method further comprising:

the firmware socket module (1) streaming the financial market data into the reconfigurable logic device from the shared memory via the DMA transfers, and (2) providing the streaming financial market data to the firmware application module pipeline; and

the firmware application module pipeline computing a plurality of VWAPs for a plurality of the financial instruments associated with the streaming financial market data that was provided to the firmware application module pipeline.

37. The method of claim 36 further comprising:

the firmware socket module providing both command data and the streaming financial market data to the firmware application module pipeline; and

the firmware application module pipeline arranging itself in accordance with the command data to control how the firmware application module operates.

38. The method of claim 37 wherein the reconfigurable logic device is in communication with the processor via a bus, and wherein the processor, bus, and reconfigurable logic device are part of a ticker plant, the method further comprising;

the processor generating the command data; and

the reconfigurable logic device accessing the command data and the streaming financial market data via the bus.

39. The method of claim 21 wherein the executing step further comprises:

the processor normalizing financial market data within the streaming financial market data;

wherein the using step comprises the processor using the shared memory to store the normalized financial market data; and

wherein the facilitating step comprises the processor facilitating DMA transfers of the normalized financial market data to the reconfigurable logic device from the shared memory.

40. The method of claim 39 wherein the shared memory comprises first shared memory that is mapped into the kernel space and the user space and second shared memory that is mapped into the kernel space and the user space, and wherein the executing step further comprises:

a first driver executing within the kernel space of the operating system while the operating system is in the kernel mode, wherein the first driver executing step comprises the first driver (1) maintaining a kernel level interface into the network protocol stack, and (2) copying the streaming financial market data from the network protocol stack into the first shared memory without a transition to the user mode; and

user mode code executing within the user space of the operating system, wherein the user mode code executing step comprises the user mode code (1) accessing financial market data from the first shared memory, (2) normalizing the accessed financial market data, and (3) writing the normalized financial market data to the second shared memory.

41. The method of claim 40 wherein the processor executing step further comprises:

a second driver executing within the kernel space of the operating system while the operating system is in the kernel mode, the second driver executing comprising the second driver facilitating the DMA transfers of the normalized financial market data from the second shared memory to the reconfigurable logic device.

42. The method of claim 41 wherein the user mode code comprises a plurality of threads, each thread normalizing a different group of the accessed financial market data independently of the other threads.

43. The method of claim 22 wherein the executing step further comprises:

a driver executing within the kernel space of the operating system while the operating system is in the kernel mode, wherein the driver executing step comprises The driver (1) reading financial market data that includes a plurality of the computed VWAPs from the memory in which the computed VWAPs are stored, and (2) selectively routing the read financial market data that includes a plurality of the computed VWAPs for delivery to a plurality of clients via a path that is wholly within the kernel space.

44. The method of claim 43 wherein the driver comprises a plurality of drivers executing within the kernel space of the operating system while the operating system is in the kernel mode.

45. The method of claim 21 wherein the reconfigurable logic device comprises a field programmable gate array (FPGA).

46. The method of claim 21 wherein the shared memory comprises a ring buffer.