APPARATUS, METHOD AND SYSTEM FOR USING SHADOW DRIVES FOR ALTERNATIVE DRIVE COMMANDS

• US 20140136768A1
• Filed: 01/17/2014
• Published: 05/15/2014
• Est. Priority Date: 03/02/2011
• Status: Active Grant

• Current Assignee: Innovations In Memory LLC
• Original Assignee: Violin Memory Incorporated
• Inventors: Iglesia, Erik de la
• Granted Patent: US 9,195,407 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD

Abstract

A storage processor is configured to identify a first disk drive and a second shadow drive associated with the first disk drive to an initiator. The storage processor receives storage commands from an initiator. When the storage commands access the first disk drive, the storage processor issues a first storage operation to the first disk drive. When the storage commands access the second shadow drive, the storage processor issues different storage operations to the first disk drive that are not supported by the initiator.

Claims

1-3. -3. (canceled)

4. An apparatus, comprising:

a processor;

storage media communicating with a processor;

the processor configured to receive a storage command; and

, in response to the received storage command;

perform a first storage operation on the storage media when the received storage command is associated with the storage media;

or

perform a second storage operation on the storage media when the received storage command is associated with a virtual storage media corresponding to the storage media.

5. The apparatus of claim 4, wherein the virtual storage media is mapped to the storage media.

6. The apparatus of claim 4, wherein the storage media comprises a plurality of memory devices.

7. The apparatus of claim 6, wherein the second storage operation is to read data from a first memory device of the storage media and store the data on a second memory device of the storage media.

8. The apparatus of claim 7, wherein the second memory device is a cache memory.

9. The apparatus of claim 4, wherein the memory devices are semiconductor devices.

10. The apparatus of claim 9, wherein the semiconductor devices are FLASH memory.

11. The apparatus of claim 4, wherein the second storage operation is a plurality of storage operations.

12. The apparatus of claim 11, wherein the second storage operation comprises writing data to a selectable group of the memory devices.

13. The apparatus of claim 12, wherein the group of the memory devices is selected based on an amount of data associated with the second storage operation.

14. The apparatus of claim 13, wherein the group is a stripe.

15. The apparatus of claim 4, further comprising the processor further configured to:

determine a utilization of blocks of memory of a cache of data in memory devices of the storage media; and

invalidate data of selected blocks of the cache of data based on a utilization criteria.

16. The apparatus of claim 15, wherein the utilization is determined on a periodic basis.

17. The apparatus of claim 4, wherein the second storage operation is a request for a performance metric of the storage media.

18. A method, comprising:

mapping memory devices of a plurality of memory devices to virtual memory devices of a plurality of virtual memory devices;

providing a processor in communication with the plurality of memory devices and configured to receive a storage command;

receiving the storage command from an initiator; and

if the storage command is associated with a memory device of the plurality of memory devices,

initiating a first storage operation on the memory device;

or

if the storage command is associated with a virtual memory device;

initiating a second storage operation on the memory device mapped to the virtual memory device.

19. The method of claim 18, wherein the second storage operation includes reading data from the mapped memory device of the plurality of memory devices and storing data read from the mapped memory device in another memory device of the plurality of memory devices.

20. The apparatus of claim 19, further comprising:

designating at least one memory memory device of the plurality of memory devices as a cache device for storing data,

determining a utilization of blocks of memory of the cache device; and

invalidating stored data of selected blocks of memory of the cache device based on a utilization criteria.

21. The apparatus of claim 18, wherein the second storage operation is a request for a performance metric of the memory device.