INSTRUCTIONS TO PERFORM JH CRYPTOGRAPHIC HASHING IN A 256 BIT DATA PATH

• US 20140205084A1
• Filed: 12/22/2011
• Published: 07/24/2014
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Yap, Kirk S., Gopal, Vinodh, Guilford, James D., Ozturk, Erdinc, Gulley, Sean M., Feghali, Wajdi K., Dixon, Martin G., Wolrich, Gilbert M.
• Granted Patent: US 9,270,460 B2
• Time in Patent Office: Days
• US Class Current: 380/28
• CPC Class Codes: G06F 21/602 Providing cryptographic facilities or services
• CPC Class Codes: G06F 9/30007 to perform operations on data operands
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3893 controlled in tandem, e.g. multiplier-accumulator
• CPC Class Codes: H04L 9/14 using a plurality of keys or algorithms
• CPC Class Codes: H04L 9/3239 involving non-keyed hash functions, e.g. modification detection codes [MDCs], MD5, SHA or RIPEMD

Abstract

A method is described. The method includes executing one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.

Claims

1. A method of performing a process in a computer processor, comprising:

executing one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state; and

executing one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.

2. The method of claim 1 further comprising storing JH state bits consecutively in a plurality of source registers before executing the JH_SBOX_L instruction.

3. The method of claim 2 further comprising:

executing the JH_SBOX_L instruction a first time to perform the S-Box mappings and the L transformation on a first component of the JH state stored in a first source register;

executing the JH_SBOX_L instruction a second time to perform the S-Box mappings and the L transformation on a second component of the JH state stored in a second source register;

executing the JH_SBOX_L instruction a third time to perform the S-Box mappings and the L transformation on a third component of the JH state stored in a third source register; and

executing the JH_SBOX_L instruction a fourth time to perform the S-Box mappings and the L transformation on a fourth component of the JH state stored in a fourth source register.

4. The method of claim 3 further comprising:

storing the results of the first execution of the JH_SBOX_L instruction in a first destination register as first JH state results;

storing the results of the second execution of the JH_SBOX_L instruction in a second destination register as second JH state results;

storing the results of the third execution of the JH_SBOX_L instruction in a third destination register as third JH state results; and

storing the results of the fourth execution of the JH_SBOX_L instruction in a fourth destination register as fourth JH state results.

5. The method of claim 4 wherein execution of the JH_P instruction further comprises:

retrieving JH state results from two of the destination registers; and

performing the permutation function on the JH state results from the two destination registers.

6. The method of claim 5 wherein execution of the JH_P instruction further comprises:

performing a first permutation function on the first JH state results and the second JH results;

performing a second permutation function on the third JH state results and the fourth JH results;

performing a third permutation function on the first JH state results and the second JH results; and

performing a fourth permutation function on the third JH state results and the fourth JH results.

7. An apparatus comprising:

a plurality of data registers; and

an execution unit coupled with the plurality of the data registers, to execute one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state and one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.

8. The apparatus of claim 7 wherein the plurality of data registers includes source registers to consecutively store JH state bits.

9. The apparatus of claim 8 wherein the execution unit executes JH_SBOX_L instruction a first time to perform the S-Box mappings and the L transformation on a first component of the JH state stored in a first source register, a second time to perform the S-Box mappings and the L transformation on a second component of the JH state stored in a second source register, a third time to perform the S-Box mappings and the L transformation on a third component of the JH state stored in a third source register and a fourth time to perform the S-Box mappings and the L transformation on a fourth component of the JH state stored in a fourth source register.

10. The apparatus of claim 9 wherein the execution unit stores the results of the first execution of the JH_SBOX_L instruction in a first destination register as first JH state results, stores the results of the second execution of the JH_SBOX_L instruction in a second destination register as second JH state results, stores the results of the third execution of the JH_SBOX_L instruction of in a third destination register as third JH state results and stores the results of the fourth execution of the JH_SBOX_L instruction of the in a fourth destination register as fourth JH state results.

11. The apparatus of claim 10 wherein the execution unit retrieves JH state results from two of the destination registers and performs the permutation function on the JH state results from the two destination registers.

12. The apparatus of claim 11 wherein the execution unit performs a first permutation function on the first JH state results and the second JH results, performs a second permutation function on the third JH state results and the fourth JH results, performs a third permutation function on the first JH state results and the second JH results and performs a fourth permutation function on the third JH state results and the fourth JH results

13. An article of manufacture comprising:

a machine-readable storage medium including one or more solid data storage materials, the machine-readable storage medium storing instructions, which when executed causes a processor to;

execute one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state; and

execute one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.

14. The article of manufacture of claim 13 wherein the machine-readable storage medium stores instructions, which when executed further causes the processor to:

execute the JH_SBOX_L instruction a first time to perform the S-Box mappings and the L transformation on a first component of the JH state stored in a first source register;

execute the JH_SBOX_L instruction a second time to perform the S-Box mappings and the L transformation on a second component of the JH state stored in a second source register;

execute the JH_SBOX_L instruction a third time to perform the S-Box mappings and the L transformation on a third component of the JH state stored in a third source register; and

execute the JH_SBOX_L instruction a fourth time to perform the S-Box mappings and the L transformation on a fourth component of the JH state stored in a fourth source register.

15. The article of manufacture of claim 14 wherein the machine-readable storage medium stores instructions, which when executed further causes the processor to:

store the results of the first execution of the JH_SBOX_L instruction of in a first destination register as first JH state results;

store the results of the second execution of the JH_SBOX_L instruction in a second destination register as second JH state results;

store the results of the third execution of the JH_SBOX_L instruction in a third destination register as third JH state results; and

store the results of the fourth execution of the JH_SBOX_L instruction in a fourth destination register as fourth JH state results.

16. The article of manufacture of claim 15 wherein the machine-readable storage medium stores instructions, which when executed further causes the processor to:

perform a first permutation function on the first JH state results and the second JH results;

perform a second permutation function on the third JH state results and the fourth JH results;

perform a third permutation function on the first JH state results and the second JH results; and

perform a fourth permutation function on the third JH state results and the fourth JH results.

17. A method of performing a process in a computer processor, comprising:

executing one or more JH_SBOX instructions to perform S-Box mappings on a JH state; and

executing one or more JH_LTRANSFORM instructions to perform a linear (L) transformation on the JH state once the S-Box mappings have been performed.

18. The method of claim 17 further comprising:

storing a first set of odd nibbles of JH state in a first register prior to executing the JH_SBOX instruction;

storing a second set of odd nibbles of JH state in a second register;

storing a first set of even nibbles of JH state in a third register; and

storing a second set of even nibbles of JH state in a fourth register.

19. The method of claim 18 further comprising:

executing the JH_SBOX instruction a first time to perform the S-Box mappings on the first set of odd nibbles;

executing the JH_SBOX instruction a second time to perform the S-Box mappings on the second set of odd nibbles;

executing the JH_SBOX instruction a third time to perform the S-Box mappings on the first set of even nibbles; and

executing the JH_SBOX instruction a fourth time to perform the S-Box mappings on the second set of even nibbles.

20. The method of claim 19 further comprising:

storing the results of the first execution of the JH_SBOX instruction in a first destination register as first odd nibbles results;

storing the results of the second execution of the JH_SBOX instruction in a second destination register as second odd nibbles results;

storing the results of the third execution of the JH_SBOX instruction in a third destination register as first even nibbles results; and

storing the results of the fourth execution of the JH_SBOX instruction in a fourth destination register as second even nibbles results.

21. The method of claim 20 wherein execution of the JH_LTRANSFORM instruction further comprises:

performing a first L transformation on the first even nibbles results;

performing a second L transformation on the second even nibbles results;

performing a third L transformation on the first odd nibbles results; and

performing a fourth L transformation on the second odd nibbles results.

22. The method of claim 21 further comprising performing a swap operation performing the L transformations.

23. The method of claim 21 wherein the swap operation comprises one of swapping adjacent even nibbles, swapping even nibble pairs, swapping even groups of 4 nibbles, swapping even groups of 8 nibbles, swapping even groups of 16 nibbles, swapping even groups of 32 nibbles and swapping even groups of 64 nibbles.

24-33. -33. (canceled)