Capacitors in Integrated Circuits and Methods of Fabrication Thereof

• US 20140273394A1
• Filed: 03/13/2013
• Published: 09/18/2014
• Est. Priority Date: 03/13/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Roehner, Michael, Aresu, Stefano
• Granted Patent: US 9,508,788 B2
• Time in Patent Office: Days
• US Class Current: 438/382
• CPC Class Codes: H01L 21/707 of thin-film circuits or parts thereof
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In one embodiment, a capacitor includes a first row including a first capacitor element and a second capacitor element coupled in parallel, and a second row including a third capacitor element and a fourth capacitor element coupled in parallel. The first row is coupled in series with the second row. In a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element. In the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element. The first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.

Claims

1. A method of making a capacitor array, the method comprising:

forming a first column comprising a first capacitor element and a second capacitor element coupled in series; and

forming a second column comprising a third capacitor element and a fourth capacitor element coupled in series, wherein the first column is coupled in parallel with the second column, wherein the second capacitor element is disposed between the first capacitor element and the fourth capacitor element within a metallization level, wherein the fourth capacitor element is disposed between the second capacitor element and the third capacitor element within the metallization level.

2. The method of claim 1, wherein the first capacitor element comprises a first plate and a second plate, wherein the second capacitor element comprises a third plate and a fourth plate, wherein the second plate and the third plate comprise a common metal line.

3. The method of claim 2, wherein the common metal line is floating.

4. The method of claim 2, wherein the first plate is coupled to the second plate through a first resistor, wherein the third plate is coupled to the fourth plate through a second resistor.

5. The method of claim 4, wherein the capacitor array comprises a poly silicon line disposed below the first and the second capacitor elements over a workpiece, wherein the first resistor comprises a first portion of the poly silicon line, and wherein the second resistor comprises a second portion of the poly silicon line.

6. A method of making a device, the method comprising:

providing a first circuit design including a single capacitor having a first capacitance and a first area;

generating a second circuit design by replacing the single capacitor with a capacitor array, the capacitor array comprising;

a plurality of columns comprising capacitor elements in series, the plurality of columns coupled in parallel to form a plurality of rows, wherein the capacitance of each capacitor element in the plurality of columns has a value equal or smaller than the value of the first capacitance, wherein each capacitor element in the plurality of columns has an area less than the first area; and

fabricating a circuit with the second circuit design comprising the capacitor array in a metallization layer over a workpiece.

7. The method of claim 6, wherein the number of rows in the plurality of rows is the same as the number of columns in the plurality of columns.

8. The method of claim 6, wherein the capacitor array is a vertical parallel plate capacitor array.

9. The method of claim 6, wherein a total area of the capacitor array is substantially similar to a total area of the single capacitor.

10. The method of claim 6, wherein the first circuit design comprises other circuitry coupled to the single capacitor, and wherein the second circuit design comprises the other circuitry coupled to the capacitor array in a same way as the single capacitor.

11. A method of making a device, the method comprising:

providing a first circuit design including a single capacitor having a first capacitance;

generating a second circuit design by replacing the single capacitor with a capacitor array, the capacitor array comprising;

a plurality of columns comprising capacitor elements in series, the plurality of columns coupled in parallel to form a plurality of rows, wherein the capacitance of each capacitor element in the plurality of columns has a value of the first capacitance multiplied by a scaling ratio, wherein the scaling ratio is a total number of elements in a column in the plurality of columns divided by a total number of elements in a row in the plurality of rows; and

fabricating a circuit with the second circuit design comprising the capacitor array in a metallization layer over a workpiece.

12. The method of claim 11, wherein the single capacitor has a first area, and wherein each capacitor element in the plurality of columns has an area less than the first area.

13. The method of claim 12, wherein a total area of the capacitor array is substantially similar to a total area of the single capacitor.

14. The method of claim 11, wherein the capacitor array is a vertical parallel plate capacitor array.

15. The method of claim 11, wherein the first circuit design comprises other circuitry coupled to the single capacitor, and wherein the second circuit design comprises the other circuitry coupled to the capacitor array in a same way as the single capacitor.

16. A method of making a device, the method comprising:

providing a first circuit design including a single capacitor having a first capacitance;

generating a second circuit design by replacing the single capacitor with a capacitor array having the first capacitance, the capacitor array comprising;

a first column comprising a first capacitor element and a second capacitor element coupled in series,

a second column comprising a third capacitor element and a fourth capacitor element coupled in series, wherein the first column is coupled in parallel with the second column; and

fabricating a circuit with the second circuit design comprising the capacitor array over a workpiece, wherein the first, the second, the third, and the fourth capacitor elements are disposed in a same metallization layer, wherein the second capacitor element is disposed between the first capacitor element and the fourth capacitor element within a metallization level, wherein the fourth capacitor element is disposed between the second capacitor element and the third capacitor element within the metallization level.

17. The method of claim 16, wherein the first column comprises a fifth capacitor element in series with the first and the second capacitor elements, and wherein the second column comprises a sixth capacitor element in series with the third and the fourth capacitor elements.

18. The method of claim 17, wherein the fifth capacitor element is disposed between the first capacitor element and the second capacitor element, wherein the sixth capacitor element is disposed between the third capacitor element and the fourth capacitor element.

19. The method of claim 16, wherein the first capacitor element comprises a first plate and a second plate, wherein the second capacitor element comprises a third plate and a fourth plate, wherein the second plate and the third plate comprise a common metal line.

20. The method of claim 19, wherein the common metal line is floating.

21. The method of claim 19, wherein the first plate is coupled to the second plate through a first resistor, wherein the third plate is coupled to the fourth plate through a second resistor.

22. The method of claim 21, wherein the circuit comprises a poly silicon line disposed below the first and the second capacitor elements over the workpiece, wherein the first resistor comprises a first portion of the poly silicon line, and wherein the second resistor comprises a second portion of the poly silicon line.

23. The method of claim 22, wherein the first and the second resistors comprise a resistive device comprising a poly silicon line, a diffusion area, or an active device.

24. The method of claim 16, wherein the capacitor array is a vertical parallel plate capacitor array.

25. A capacitor comprising:

a first row comprising a first capacitor element and a second capacitor element coupled in parallel; and

a second row comprising a third capacitor element and a fourth capacitor element coupled in parallel, wherein the first row is coupled in series with the second row, wherein, in a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element, wherein, in the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element, wherein the first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.

26. The capacitor of claim 25, wherein the first, the second, the third, and the fourth capacitor elements have a same first capacitance.

27. The capacitor of claim 25, wherein the first row comprises a fifth capacitor element coupled in parallel to the first and the second capacitor elements, wherein the second row comprises a sixth capacitor element coupled in parallel to the third and the fourth capacitor elements.

28. The capacitor of claim 27, wherein the first row comprises a fifth capacitor element coupled in parallel to the first and the second capacitor elements, wherein the fourth capacitor element is disposed between the third capacitor element and the fifth capacitor element.

29. The capacitor of claim 25, wherein the capacitor is a vertical parallel plate capacitor array.

30. The capacitor of claim 25, wherein the first capacitor element comprises a first metal line and a second metal line, wherein the second capacitor element comprises the second metal line and a third metal line, wherein the first metal line of the first capacitor element is coupled to the third metal line of the second capacitor element by a first vertical metal line oriented in a direction perpendicular to first and the third metal lines of the first and the second capacitor elements.

31. A capacitor comprising:

a first conductive line oriented along a first direction disposed over a substrate in a first metal level;

a second conductive line oriented along the first direction disposed over the substrate in the first metal level, and capacitively coupled to the first conductive line;

a third conductive line oriented along the first direction disposed over the substrate in the first metal level, the second conductive line disposed between the first and the third conductive lines;

a first perpendicular conductive line oriented along a second direction disposed in a second metal level over the first metal level, wherein the first conductive line is coupled to the first perpendicular conductive line, wherein the first direction is perpendicular to the second direction; and

a second perpendicular conductive line oriented along the second direction disposed in the second metal level, wherein the second perpendicular conductive line is coupled to the third conductive line, wherein the first perpendicular conductive line is coupled to a first potential node, wherein the second perpendicular conductive line is coupled to a second potential node.

32. The capacitor of claim 31, wherein the third conductive line is capacitively coupled to the second conductive line.

33. The capacitor of claim 31, wherein the second conductive line is floating.

34. The capacitor of claim 31, wherein the second conductive line is coupled to the first potential node through a first resistor and to the second potential node through a second resistor.

35. The capacitor of claim 34, wherein the first resistor is a first portion of a poly silicon line, wherein the second resistor is a second portion of the poly silicon line.

36. The capacitor of claim 34, wherein the first and the second resistors comprise a resistive device comprising a poly silicon line, a diffusion area, or an active device.

37. The capacitor of claim 31, further comprising:

a fourth conductive line oriented along the first direction disposed over the substrate in the first metal level, wherein the fourth conductive line is capacitively coupled to the third conductive line; and

a fifth conductive line oriented along the first direction disposed over the substrate in the first metal level, wherein the fifth conductive line is capacitively coupled to the fourth conductive line, wherein the fourth conductive line is disposed between the third and the fifth conductive lines, wherein the fifth conductive line is coupled to the second perpendicular conductive line.

38. The capacitor of claim 37, further comprising a third perpendicular conductive line oriented along the second direction disposed in the second metal level, and wherein the second and the fourth conductive lines are coupled to the third perpendicular conductive line.

39. The capacitor of claim 38, further comprising:

a sixth conductive line oriented along the first direction disposed over the substrate in the first metal level, wherein the sixth conductive line is capacitively coupled to the fifth conductive line; and

a seventh conductive line oriented along the first direction disposed over the substrate in the first metal level, wherein the seventh conductive line is capacitively coupled to the sixth conductive line, wherein the sixth conductive line is disposed between the fifth and the seventh conductive lines.

40. The capacitor of claim 39, wherein the sixth conductive line is coupled to a fourth perpendicular conductive line, and wherein the seventh conductive line is coupled to the second perpendicular conductive line.

41. The capacitor of claim 39, wherein the sixth conductive line is coupled to the third perpendicular conductive line, and wherein the seventh conductive line is coupled to the second perpendicular conductive line.

42. The capacitor of claim 31, further comprising:

a fourth conductive line oriented along the first direction disposed over the substrate in the first metal level, wherein the fourth conductive line is disposed between the second conductive line and the third conductive line, wherein the fourth conductive line is capacitively coupled to the second conductive line and the third conductive line.