MEMORY SYSTEM AND MEMORY CONTROLLER

• US 20140281164A1
• Filed: 09/06/2013
• Published: 09/18/2014
• Est. Priority Date: 03/14/2013
• Status: Abandoned Application

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: NISHIYAMA, Takahide
• Application Number:
  US14/020,305
• Publication Number:
  US 20140281164A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

According to one embodiment, a memory system includes a plurality of nonvolatile semiconductor memories including a plurality of memory cell transistors for holding data, and holding position information indicating a position of a defective memory cell transistor incapable of normally holding data and a position of a substitute portion for the defective memory cell transistor.

Claims

1. A memory system comprising:

a plurality of nonvolatile semiconductor memories including a plurality of memory cell transistors for holding data, and holding defect position information indicating a position of a defective memory cell transistor incapable of normally holding data and a position of a substitute portion for the defective memory cell transistor;

a first controller which selects a nonvolatile semiconductor memory to be accessed;

a first memory which stores the defect position information held in the nonvolatile semiconductor memories and corresponding to each nonvolatile semiconductor memory;

a second memory which holds a plurality of codes containing at least an instruction portion, and first information indicating the nonvolatile semiconductor memory to be accessed by the instruction portion, and outputs the code corresponding to the nonvolatile semiconductor memory selected by the first controller;

a decoder which decodes the code supplied from the second memory, and reads out the instruction portion and the first information;

a third memory which stores the defect position information of one of the nonvolatile semiconductor memories;

a fourth memory which stores second information indicating the nonvolatile semiconductor memory corresponding to the defect position information stored in the third memory; and

a second controller which controls the first memory and the third memory,

wherein the decoder reads out the second information from the fourth memory, and compares the first information with the second information, and

notifies the second controller of a result of the comparison, and

the second controller reads out, when receiving a notification indicating that the first information differs from the second information, defect position information corresponding to the nonvolatile semiconductor memory to be accessed by the instruction portion, from the first memory based on the first information,

updates the defect position information stored in the third memory to the readout defect position information, and

executes an operation based on the instruction portion by using the defect position information stored in the third memory, after the defect position information stored in the third memory is updated or when receiving a notification indicating that the first information and the second information are the same.

2. The system according to claim 1, further comprising a third controller which controls connection to the nonvolatile semiconductor memory by the second controller.

3. The system according to claim 2, wherein the third controller stops transmission/reception of data to/from the nonvolatile semiconductor memory while the defect position information stored in the third memory is updating.

4. The system according to claim 1, wherein

when writing data in the nonvolatile semiconductor memory, the second controller supplies dummy data to the defective memory cell transistor, and supplies, to the substitute portion, data to be supplied to the defective memory cell transistor, by using the defect position information stored in the third memory, and

when reading out data from the nonvolatile semiconductor memory, the second controller discards data read out from the defective memory cell transistor, and reads out data from the substitute portion, by using the defect position information stored in the third memory.

5. The system according to claim 1, wherein after the defect position information in the third memory is updated, the decoder updates the second information in the fourth memory to the first information.

6. The system according to claim 1, wherein the third memory comprises a flip-flop.

7. The system according to claim 1, wherein the first memory is a volatile semiconductor memory.

8. The system according to claim 1, wherein

the nonvolatile semiconductor memory comprises a plurality of pages each including a plurality of memory cell transistors, and

a substitute portion for the defective memory cell transistor of a predetermined page is formed in the predetermined page.

9. A memory controller for accessing a plurality of nonvolatile semiconductor memories including a plurality of memory cell transistors for holding data, and holding defect position information indicating a position of a defective memory cell transistor incapable of normally holding data and a position of a substitute portion for the defective memory cell transistor,

the memory controller comprising:

a first controller which selects a nonvolatile semiconductor memory to be accessed;

a first memory which stores the defect position information held in the nonvolatile semiconductor memories and corresponding to each nonvolatile semiconductor memory;

a second memory which holds a plurality of codes each containing at least an instruction portion, and first information indicating the nonvolatile semiconductor memory to be accessed by the instruction portion, and outputs the code corresponding to the nonvolatile semiconductor memory selected by the first controller;

a decoder which decodes the code supplied from the second memory, and read out the instruction portion and the first information;

a third memory which stores the defect position information of one of the nonvolatile semiconductor memories;

a fourth memory which stores second information indicating the nonvolatile semiconductor memory corresponding to the defect position information stored in the third memory; and

a second controller which controls the first memory and the third memory,

wherein the decoder reads out the second information from the fourth memory, and compares the first information with the second information, and

notifies the second controller of a result of the comparison, and

the second controller reads out, when receiving a notification indicating that the first information differs from the second information, defect position information corresponding to the nonvolatile semiconductor memory to be accessed by the instruction portion, from the first memory based on the first information,

updates the defect position information stored in the third memory to the readout defect position information, and

executes an operation based on the instruction portion by using the defect position information stored in the third memory, after the defect position information stored in the third memory is updated or when receiving a notification indicating that the first information and the second information are the same.

10. The controller according to claim 9, further comprising a third controller which controls connection to the nonvolatile semiconductor memory by the second controller.

11. The controller according to claim 10, wherein the third controller stops transmission/reception of data to/from the nonvolatile semiconductor memory while the defect position information stored in the third memory is updating.

12. The controller according to claim 9, wherein

when writing data in the nonvolatile semiconductor memory, the second controller supplies dummy data to the defective memory cell transistor, and supplies, to the substitute portion, data to be supplied to the defective memory cell transistor, by using the defect position information stored in the third memory, and

when reading out data from the nonvolatile semiconductor memory, the second controller discards data read out from the defective memory cell transistor, and reads out data from the substitute portion, by using the defect position information stored in the third memory.

13. The controller according to claim 9, wherein after the defect position information in the third memory is updated, the decoder updates the second information in the fourth memory to the first information.

14. The controller according to claim 9, wherein the third memory comprises a flip-flop.

15. The controller according to claim 9, wherein the first memory is a volatile semiconductor memory.

16. The controller according to claim 9, wherein

the nonvolatile semiconductor memory comprises a plurality of pages each including a plurality of memory cell transistors, and

a substitute portion for the defective memory cell transistor of a predetermined page is formed in the predetermined page.