COMPENSATION CIRCUIT FOR USE WITH INPUT BUFFER AND METHOD OF OPERATING THE SAME

• US 20150016195A1
• Filed: 07/09/2014
• Published: 01/15/2015
• Est. Priority Date: 07/09/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jun Bae, YU, Hye Seung
• Granted Patent: US 9,306,569 B2
• Time in Patent Office: Days
• US Class Current: 365/189.05
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H03K 19/00369 Modifications for compensating variations of temperature, supply voltage or other physical parameters
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 19/018528 with at least one differential stage

Abstract

A compensation circuit for use with an input buffer includes an input buffer configured to amplify an input signal and output a compensated signal. A process detector includes a replica of the input buffer. The process detector is configured to output at least one comparison signal indicating a variation in the input buffer. The input buffer controls an output signal based on the at least one comparison signal.

Claims

1. A compensation circuit for use with an input buffer, the compensation circuit comprising:

an input buffer configured to amplify an input signal and output a compensated signal; and

a process detector including a replica of the input buffer, the process detector configured to output at least one comparison signal indicating a variation in the input buffer,

wherein the input buffer is configured to control an output signal based on the at least one comparison signal.

2. The compensation circuit of claim 1, wherein the input buffer is configured to control a bias voltage of an output terminal according to the at least one comparison signal.

3. The compensation circuit of claim 1, wherein the input buffer comprises an input buffer differential amplifier configured to receive and differentially amplify a reference voltage and the input signal, and the replica comprises a replica buffer differential amplifier including two input terminals to which the reference voltage is applied, the replica buffer differential amplifier configured to output a replica voltage.

4. The compensation circuit of claim 3, wherein the input buffer further comprises an output adjust unit configured to decrease a bias voltage of an output terminal when the variation is slow-fast (SF) and to increase the bias voltage of the output terminal when the variation is fast-slow (FS).

5. The compensation circuit of claim 3, further comprising:

a first comparator configured to compare the replica voltage with a first reference voltage and output a first comparison signal according to a result of the comparison; and

a second comparator configured to compare the replica voltage with a second reference voltage and output a second comparison signal according to a result of the comparison.

6. The compensation circuit of claim 5, further comprising:

a first storage unit configured to store the first comparison signal; and

a second storage unit configured to store the second comparison signal.

7. The compensation circuit of claim 5, wherein the input buffer differential amplifier comprises:

a pull-down unit connected with a first pull-down node having a bias voltage that is less than or equal to the bias voltage of the output terminal and a second pull-down node having a bias voltage that is less than the bias voltage of the first pull-down node, the pull-down unit selectively switched according to the first comparison signal; and

a pull-up unit connected with a first pull-up node having a bias voltage that is equal to or greater than the bias voltage of the output terminal and a second pull-up node having a bias voltage that is greater than the bias voltage of the first pull-up node, the pull-up unit selectively switched according to the second comparison signal.

8. The compensation circuit of claim 5, wherein the first reference voltage and the second reference voltage are set based on a preset condition of process corners of the input buffer.

9. The compensation circuit of claim 3, wherein each of the input buffer differential amplifier and the replica buffer differential amplifier includes a Bazes type buffer, an N-P type buffer, or a combination of the Bazes type buffer and the N-P type buffer.

10. A semiconductor device comprising the compensation circuit of the input buffer of claim 1.

11. The semiconductor device of claim 10, which is a dynamic random access memory (DRAM) configured to receive an address signal, a command signal, and a data input signal, wherein the input buffer amplifies the address signal, the command signal, or the data input signal.

12. A method of compensating for a variation in an input buffer of a semiconductor device, the method comprising:

detecting a variation in the input buffer by using a replica of the input buffer; and

controlling an output of the input buffer based on the detected variation.

13. The method of claim 12, wherein detecting the variation comprises comparing an output of the replica with preset reference voltages and outputting logic levels according to a result of the comparison.

14. The method of claim 12, wherein detecting the variation further comprises storing the logic levels in registers, respectively, and wherein the output of the input buffer is controlled based on the logic levels stored in the registers.

15. The method of claim 12, wherein the semiconductor device is a dynamic random access memory (DRAM), and wherein detecting the variation is performed together with ZQ calibration of the DRAM.

16. A variation compensation circuit comprising:

a first buffer configured to receive an input signal and a reference signal through two input terminals, respectively, and output an output signal;

a second buffer having substantially the same configuration as the first buffer, the second buffer configured to receive the reference signal through two input terminals and output a replica voltage;

a first comparator configured to compare the replica voltage with a first reference voltage and output a first comparison signal; and

a second comparator configured to compare the replica voltage with a second reference voltage and output a second comparison signal, wherein the first buffer is configured to adjust the output signal depending on the first comparison signal and the second comparison signal.

17. The circuit of claim 16, wherein the first buffer comprises a differential amplifier.

18. The circuit of claim 16, further comprising:

a first storage unit configured to store the first comparison signal; and

a second storage unit configured to store the second comparison signal.

19. The circuit of claim 16, wherein the first reference voltage and the second reference voltage are set based on a preset condition of process corners of the first buffer.

20. The circuit of claim 17, wherein the differential amplifier includes a Bazes type buffer or an N-P type buffer.