Compensation circuit for use with input buffer and method of operating the same
First Claim
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1. A compensation circuit for use with an input buffer, the compensation circuit comprising:
- an input buffer configured to amplify an input signal and output a compensated signal;
a process detector including a replica of the input buffer, the process detector configured to output at least one comparison signal indicating a variation in the input buffer,wherein the input buffer is configured to control an output signal based on the at least one comparison signal,wherein the input buffer comprises an input buffer differential amplifier configured to receive and differentially amplify a reference voltage and the input signal, and the replica comprises a replica buffer differential amplifier including two input terminals to which the reference voltage is applied, the replica buffer differential amplifier configured to output a replica voltage, andwherein the input buffer further comprises an output adjust unit configured to decrease a bias voltage of an output terminal when the variation is slow-fast (SF) and to increase the bias voltage of the output terminal when the variation is fast-slow (FS).
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Abstract
A compensation circuit for use with an input buffer includes an input buffer configured to amplify an input signal and output a compensated signal. A process detector includes a replica of the input buffer. The process detector is configured to output at least one comparison signal indicating a variation in the input buffer. The input buffer controls an output signal based on the at least one comparison signal.
19 Citations
17 Claims
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1. A compensation circuit for use with an input buffer, the compensation circuit comprising:
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an input buffer configured to amplify an input signal and output a compensated signal; a process detector including a replica of the input buffer, the process detector configured to output at least one comparison signal indicating a variation in the input buffer, wherein the input buffer is configured to control an output signal based on the at least one comparison signal, wherein the input buffer comprises an input buffer differential amplifier configured to receive and differentially amplify a reference voltage and the input signal, and the replica comprises a replica buffer differential amplifier including two input terminals to which the reference voltage is applied, the replica buffer differential amplifier configured to output a replica voltage, and wherein the input buffer further comprises an output adjust unit configured to decrease a bias voltage of an output terminal when the variation is slow-fast (SF) and to increase the bias voltage of the output terminal when the variation is fast-slow (FS). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of compensating for a variation in an input buffer of a semiconductor device, the method comprising:
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detecting a variation in the input buffer by using a replica of the input buffer; and controlling an output of the input buffer based on the detected variation, wherein the input buffer comprises an input buffer differential amplifier configured to receive and differentially amplify a reference voltage and an input signal, and the replica comprises a replica buffer differential amplifier configured to output a replica voltage, comparing the replica voltage with a first reference voltage and output a first comparison signal according to a result of the comparison; comparing the replica voltage with a second reference voltage and output a second comparison signal according to a result of the comparison; storing the first comparison signal; and storing the second comparison signal. - View Dependent Claims (11, 12, 13)
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14. A variation compensation circuit comprising:
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a first buffer configured to receive an input signal and a reference signal through two input terminals, respectively, and output an output signal; a second buffer having substantially the same configuration as the first buffer, the second buffer configured to receive the reference signal through two input terminals and output a replica voltage; a first comparator configured to compare the replica voltage with a first reference voltage and output a first comparison signal; a second comparator configured to compare the replica voltage with a second reference voltage and output a second comparison signal, wherein the first buffer is configured to adjust the output signal depending on the first comparison signal and the second comparison signal; a first storage unit configured to store the first comparison signal; and a second storage unit configured to store the second comparison signal. - View Dependent Claims (15, 16, 17)
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Specification