Delay Compensation for Variable Cable Length

• US 20150043697A1
• Filed: 08/12/2013
• Published: 02/12/2015
• Est. Priority Date: 08/12/2013
• Status: Active Grant

• Current Assignee: Schweitzer Engineering Laboratories, Incorporated
• Original Assignee: Schweitzer Engineering Laboratories, Incorporated
• Inventors: Achanta, Srinivas, Ahsan, Hidayatullah
• Granted Patent: US 9,319,100 B2
• Time in Patent Office: Days
• US Class Current: 375/371
• CPC Class Codes: H02J 13/00 Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
• CPC Class Codes: H02J 13/00002 characterised by monitoring
• CPC Class Codes: H02J 13/00034 the elements or equipment being or involving an electric power substation
• CPC Class Codes: H04B 3/04 Control of transmission; Equalising
• CPC Class Codes: H04J 3/0638 Clock or time synchronisation among nodes; Internode synchronisation synchronization for ring networks H04L12/422; data switching networks with synchronous transmission H04L12/43
• CPC Class Codes: H04J 3/065 using timestamps
• CPC Class Codes: H04J 3/0667 Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays arrangements for monitoring round trip delays in packet switching networks H04L43/0864
• CPC Class Codes: H04J 3/0697 Synchronisation in a packet node
• CPC Class Codes: Y02E 60/00 Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
• CPC Class Codes: Y04S 10/30 State monitoring, e.g. fault, temperature monitoring, insulator monitoring, corona discharge

Abstract

The present application discloses a time distribution device capable of providing a synchronized time signal to a plurality of end devices connected to the time distribution device with cables of various lengths. The time distribution device may receive a time signal, generate a time reference based on the received time signal, compensate the time reference for hardware delay, and overcompensate the time reference for a delay caused by a maximum cable length. Prior to being distributed to various end devices, each being connected with the time distribution device by cables of varying length, this overcompensated time reference may then be delayed by an amount based on the cable length connecting each respective end device such that the arrival of each of the synchronized time references at the various end devices is synchronized.

Claims

1. A method comprising:

receiving, at a time distribution device, a time signal (e.g., GPS PPS);

generating a time reference, based on the time received time signal, to be transmitted to a plurality of end devices, including;

compensating for a hardware delay of the time distribution device; and

overcompensating for a delay caused by a maximum cable length;

for each end device, adding a delay to the time reference, based on a corresponding cable length, to create a plurality of synchronized time references, wherein the delay for each end device is calculated such that the arrival of the plurality of synchronized time references at the plurality of end devices is synchronized; and

transmitting the plurality of synchronized time references, each to a respective end device of the plurality of end devices.

3. The method of claim 1, wherein generating a time reference is performed by a Field-Programmable Gate Array (FPGA).

4. The method of claim 3, wherein adding a delay to the time reference is performed by a plurality of registers of the FPGA.

5. The method of claim 4, further comprising updating the FPGA registers by a processing unit of the time distribution device based on a received cable length.

6. The method of claim 5, further comprising calculating the delay by the processing unit of the time distribution device based on the received cable length.

7. The method of claim 1, further comprising encoding time data on the time reference.

2. The method of 1, further comprising receiving a length of each of a plurality of cables connecting the plurality of end devices to the time distribution device.

8. A time distribution device for receiving and distributing a synchronized time reference to a plurality of end devices, comprising:

a receiver configured to receive a time signal;

a time reference generation component configured to generate a time reference based on the time signal, including;

compensate for a hardware delay of the time distribution device;

overcompensate for a delay caused by a maximum cable length; and

add a delay to the time reference for each of the plurality of end devices based on a corresponding cable length wherein the delay for each end device is calculated such that the arrival of the time reference at the plurality of end devices is synchronized; and

a transmitter configured to transmit the synchronized time reference to each of the plurality of end devices.

9. The time distribution device of claim 8, further comprising a user interface component configured to receive a length of each of a plurality of cables connecting the plurality of end devices to the time distribution device.

10. The time distribution device of claim 8, further comprising a processing unit configured to update the time reference generation component based on a received length of each of a plurality of cables connecting the plurality of end devices to the time distribution device.

11. The time distribution device of claim 10, wherein the processing unit is further configured to calculate the delay based on the received cable length.

12. The time distribution device of claim 8, wherein the time reference generation component comprises a frequency synthesizer configured to create the time reference based on the time signal.

13. The time distribution device of claim 8, wherein the time reference generation component comprises a Field-Programmable Gate Array (FPGA).

14. The time distribution device of claim 13, wherein the FPGA comprises a plurality of registers configured to delay the time reference.

15. The time distribution device of claim 14, further comprising a processing unit configured to update the plurality of registers based on a received length of each of a plurality of cables connecting the plurality of end devices to the time distribution device.

16. The time distribution device of claim 8, further comprising a time data encoder to encode time data from the time signal on the time reference.