SEMICONDUCTOR DEVICE HAVING AN AIRBRIDGE AND METHOD OF FABRICATING THE SAME

• US 20150102490A1
• Filed: 11/24/2014
• Published: 04/16/2015
• Est. Priority Date: 01/31/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: WHETTEN, Timothy J., RICHLING, Wayne P.
• Granted Patent: US 9,859,205 B2
• Time in Patent Office: Days
• US Class Current: 257/745
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 2224/4013 Connecting within a semiconductor or solid-state body, i.e. fly strap, bridge strap
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 23/4821 Bridge structure with air gap
• CPC Class Codes: H01L 23/5221 Crossover interconnections
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device and a method of forming an airbridge extending from a conductive area of the semiconductor device are provided. The semiconductor device includes a device pattern formed on a semiconductor substrate, a seed layer formed on the device pattern, and an airbridge formed on the seed layer, where the airbridge includes a plated conductive material and defines an opening exposing a portion of the device pattern. The semiconductor device further includes an adhesion layer formed on the airbridge layer and extending over at least a portion of sidewalls of the opening defined by the airbridge, and an insulating layer formed on the adhesion layer, where the adhesion layer enhances adhesion of the insulating layer to the plated conductive material of the airbridge.

Claims

1. A method of forming an airbridge extending from a conductive area of a semiconductor device, the method comprising:

applying a first photoresist layer on a substrate, with or without a device, and developing the first photoresist layer to form a first photoresist pattern;

applying a conductive lower layer on the first photoresist layer;

applying a conductive seed layer on the conductive lower layer;

applying a second photoresist layer on the conductive seed layer, and etching the second photoresist layer to form a second photoresist pattern;

applying a plated gold layer on the conductive seed layer using an electroplating process;

removing the second photoresist pattern to form an opening in the plated gold layer corresponding to the airbridge of the semiconductor device, the opening exposing a portion of the conductive seed layer;

removing the exposed portion of the conductive seed layer, exposing a portion of the first photoresist pattern within the opening in the plated gold layer;

partially etching the exposed portion of the first photoresist pattern using oxygen plasma, the partial etching undercutting the photoresist layer to form a gap between the plated gold layer and the first photoresist pattern at the opening in the plated gold layer;

applying an adhesion layer on the plated gold layer and the exposed portion of the first photoresist pattern, the adhesion layer having a break at the gap between the plated gold layer and the first photoresist pattern;

removing the first photoresist pattern using a solvent applied to the first photoresist pattern through the break in the adhesion layer, the solvent lifting off a portion of the adhesion layer on the exposed portion of the first photoresist pattern; and

applying an insulating layer on the adhesion layer to enhance adhesion of the insulating layer to the plated gold layer.

2. The method of claim 1, wherein the adhesion layer comprises one of titanium or tantalum.

3. The method of claim 2, wherein the adhesion layer covers at least a portion of side walls of the opening in the plated gold layer.

4. The method of claim 1, wherein removing the second photoresist pattern comprises a flood expose and develop process.

5. The method of claim 4, wherein the semiconductor device comprises one of a monolithic microwave integrated circuit (MMIC), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a pseudomorphic high electron mobility transistor (pHEMT), an enhancement-mode pseudomorphic high electron mobility transistor (E-pHEMT), a heterojunction bipolar transistor (HBT).

6. The method of claim 1, wherein the semiconductor device is formed of gallium arsenide (GaAs).

7. A semiconductor device, comprising:

a device pattern formed on a semiconductor substrate;

a seed layer formed on the device pattern;

an airbridge formed on the seed layer, the airbridge comprising a plated conductive material and defining an opening exposing a portion of the device pattern;

an adhesion layer formed on the airbridge layer and extending over at least a portion of sidewalls of the opening defined by the airbridge; and

an insulating layer formed on the adhesion layer, the adhesion layer enhancing adhesion of the insulating layer to the plated conductive material of the airbridge.

8. The device of claim 7, wherein the plated conductive material comprises gold and the insulating layer comprises silicon nitride.

9. The device of claim 8, wherein the adhesion layer comprises a conductive adhesion material.

10. The device of claim 8, wherein the seed layer comprises plated gold.

11. The device of claim 7, wherein the adhesion layer comprises titanium.

12. The device of claim 7, wherein the adhesion layer comprises tantalum.

13. The device of claim 7, wherein the adhesion layer comprises titanium oxide.

14. The device of claim 7, wherein the wherein the semiconductor device comprises a gallium arsenide (GaAs) semiconductor device.

15. The device of claim 14, wherein the semiconductor device comprises one of a monolithic microwave integrated circuit (MMIC), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a pseudomorphic high electron mobility transistor (pHEMT), an enhancement-mode pseudomorphic high electron mobility transistor (E-pHEMT), a heterojunction bipolar transistor (HBT).