SEMICONDUCTOR LIGHT EMITTING DEVICE WITH LIGHT EXTRACTION STRUCTURES

• US 20150364654A1
• Filed: 08/27/2015
• Published: 12/17/2015
• Est. Priority Date: 12/19/2007
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Koninklijke Philips N.V.
• Inventors: WIERER, Jonathan J., DAVID, Aurelien Jean Francois, CHOY, Henry Kwong-Hin
• Granted Patent: US 9,935,242 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/26 Materials of the light emitting region
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/405 Reflective materials

Abstract

Structures are incorporated into a semiconductor light emitting device which may increase the extraction of light emitted at glancing incidence angles. In some embodiments, the device includes a low index material that directs light away from the metal contacts by total internal reflection. In some embodiments, the device includes extraction features such as cavities in the semiconductor structure which may extract glancing angle light directly, or direct the glancing angle light into smaller incidence angles which are more easily extracted from the device.

Claims

1. A device comprising:

a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region;

a reflective metal contact disposed on a bottom side of the semiconductor structure and electrically connected to the p-type region; and

an oxide disposed between the reflective metal contact and the p-type region;

wherein at least a portion of a top side of the semiconductor structure is textured.

2. The device of claim 1 wherein a distance between the textured portion of the top side of the semiconductor structure and the reflective metal contact is less than 5 μ

m.

3. The device of claim 1 wherein a difference between an index of refraction of the oxide and an index of refraction of the p-type region is at least 0.4.

4. The device of claim 1 wherein the oxide is doped.

5. The device of claim 1 wherein the oxide is indium tin oxide.

6. The device of claim 1 wherein the oxide is one of InO, ZnO, Ga_xO_y, and CuO.

7. The device of claim 1 further comprising a metal layer disposed between the semiconductor structure and the oxide.

8. The device of claim 1 wherein the oxide is porous.

9. The device of claim 1 wherein the oxide comprises columns with air gaps between the columns.

10. The device of claim 1 wherein the oxide has a resistance no more than 1 Ω

-cm.

11. The device of claim 1 wherein the p-type region is a first p-type region, the device further comprising a second p-type region, wherein the oxide is disposed between the first p-type region and the second p-type region.

12. The device of claim 11 wherein the oxide is formed in a plurality of regions, the device further comprising AlInN disposed between neighboring oxide regions.

13. The device of claim 11 wherein the oxide is formed in a plurality of regions and the second p-type region is patterned to form openings aligned with the oxide regions.

14. The device of claim 11 wherein the second p-type region is disposed between the oxide and the reflective metal.

15. The device of claim 11 wherein the oxide is one of amorphous Al_xO_y and amorphous Al_xIn_yO_z.

16. A method comprising:

growing a semiconductor structure comprising a light emitting layer disposed between an n-type region and a first p-type region;

growing an additional semiconductor layer on the semiconductor structure;

growing a second p-type region on the additional semiconductor layer;

forming openings in the second p-type region that expose the additional semiconductor layer; and

after forming openings, oxidizing a portion of the additional semiconductor layer.

17. The method of claim 41 further comprising forming a reflective metal contact electrically connected to the second p-type region.

18. The method of claim 41 wherein the additional semiconductor layer is AlInN.

19. The method of claim 41 wherein oxidizing a portion of the additional semiconductor layer comprises forming oxidized regions, wherein non-oxidized portions of the additional semiconductor layer remain between oxidized regions.