Semiconductor light emitting device with light extraction structures

• US 9,935,242 B2
• Filed: 08/27/2015
• Issued: 04/03/2018
• Est. Priority Date: 12/19/2007
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Inventors: Wierer, Jonathan J., David, Aurelien Jean Francois, Choy, Henry Kwong-Hin
• Primary Examiner(s): Zarneke, David
• Application Number:
  US14/837,339
• Publication Number:
  US 20150364654A1
• Time in Patent Office: 950 Days
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/26 Materials of the light emitting region
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/405 Reflective materials

Abstract

Structures are incorporated into a semiconductor light emitting device which may increase the extraction of light emitted at glancing incidence angles. In some embodiments, the device includes a low index material that directs light away from the metal contacts by total internal reflection. In some embodiments, the device includes extraction features such as cavities in the semiconductor structure which may extract glancing angle light directly, or direct the glancing angle light into smaller incidence angles which are more easily extracted from the device.

Claims

1. A method comprising:

providing a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region, the semiconductor structure having a first surface and a second surface opposite the first surface;

forming a plurality of cavities in the first surface of the semiconductor structure, the plurality of cavities being spaced apart and extending into at least one of the n-type region and the p-type region;

roughening at least a portion of the second surface to form a plurality of features spaced apart at least a distance smaller than a distance between each of the plurality of cavities formed in the first surface;

lining the plurality of cavities with a dielectric layer;

forming at least one contact in contact with the first surface of the semiconductor structure; and

providing the semiconductor structure on a substrate such that the first surface of the semiconductor structure is adjacent the substrate.

2. The method of claim 1, wherein the contact is electrically connected to the p-type region.

3. The method of claim 1, wherein each of the plurality of cavities has a pentagon-shaped cross-section.

4. The method of claim 3, wherein sidewalls of the plurality of cavities have sidewall angles between 35°

and 55°

.

5. The method of claim 1, wherein the first surface is a surface of the p-type region and the at least one contact is at least one p-contact, or the first surface is a surface of the n-type region, and the at least one contact is at least one n-contact.

6. The method of claim 1, further comprising forming at least one other contact contacting the second surface of the semiconductor structure.

7. The method of claim 1, further comprising selecting at least one of a size, a shape and a spacing of the plurality of cavities to direct light incident on the plurality of cavities, at a range of angles greater than 70°

relative to a normal to the second surface, out of the semiconductor structure via the second surface.

8. The method of claim 1, wherein the lining the plurality of cavities with a dielectric layer comprises selecting a thickness of the dielectric layer to be a wavelength or less and to avoid optical resonances.

9. The method of claim 1, wherein the plurality of cavities are filled with air.