PIXEL ARRAY STRUCTURE AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE
First Claim
1. A manufacturing method of a pixel array structure, comprising:
- forming a doped active layer on an active layer, the doped active layer having a portion with a larger thickness and a portion with a smaller thickness;
forming a source/drain metal layer on the doped active layer and the active layer;
conducting an etching process on the source/drain metal layer, so as to form a source electrode and a drain electrode, one of which partially covers the portion of the doped active layer with a larger thickness;
conducting an etching process on the doped active layer and the active layer between the source electrode and the drain electrode, so as to form an optimized channel located between the retained portion of the doped active layer having a larger thickness and the other of the source electrode and the drain electrode.
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Accused Products
Abstract
A pixel array structure and manufacturing method thereof, an array substrate and a display device are provided. The manufacturing method of the pixel array structure includes: forming a doped active layer over an active layer, the doped active layer having a portion with a larger thickness and a portion with a smaller thickness; forming a source/drain metal layer on the doped active layer and the active layer; conducting an etching process on the source/drain metal layer, so as to form a source electrode and a drain electrode, one of which partially covers the portion of the doped active layer with a larger thickness; conducting an etching process on the doped active layer and the active layer in a region between the source electrode and the drain electrode, so as to forming an optimized channel. With the manufacturing method, the on-state current of a channel of a thin film transistor can be raised.
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Citations
16 Claims
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1. A manufacturing method of a pixel array structure, comprising:
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forming a doped active layer on an active layer, the doped active layer having a portion with a larger thickness and a portion with a smaller thickness; forming a source/drain metal layer on the doped active layer and the active layer; conducting an etching process on the source/drain metal layer, so as to form a source electrode and a drain electrode, one of which partially covers the portion of the doped active layer with a larger thickness; conducting an etching process on the doped active layer and the active layer between the source electrode and the drain electrode, so as to form an optimized channel located between the retained portion of the doped active layer having a larger thickness and the other of the source electrode and the drain electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 12, 13, 14, 15, 16)
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9. A pixel array structure, comprising:
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a base substrate and a gate electrode formed in a same layer on the base substrate; a gate insulating layer, an active layer and a doped active layer formed on the gate electrode in sequence, the doped active layer having a portion with a larger thickness and a portion with a smaller thickness; and a source/drain electrode layer over the doped active layer, which includes a source electrode and a drain electrode, wherein one of the source electrode and the drain electrode partially covers the portion of the doped active layer with a larger thickness, and an optimized channel is provided between the doped active layer retained between the source electrode and the drain electrode and the other of the source electrode and the drain electrode. - View Dependent Claims (10, 11)
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Specification