Pixel array structure having doped active layer with uneven thickness and manufacturing method thereof, array substrate and display device

• US 9,985,140 B2
• Filed: 07/18/2014
• Issued: 05/29/2018
• Est. Priority Date: 12/18/2013
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Li, Tiansheng
• Primary Examiner(s): MUSE, ISMAIL A
• Application Number:
  US14/426,298
• Publication Number:
  US 20160027930A1
• Time in Patent Office: 1,411 Days
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/127 with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A pixel array structure and manufacturing method thereof, an array substrate and a display device are provided. The manufacturing method of the pixel array structure includes: forming a doped active layer over an active layer, the doped active layer having a portion with a larger thickness and a portion with a smaller thickness; forming a source/drain metal layer on the doped active layer and the active layer; conducting an etching process on the source/drain metal layer, so as to form a source electrode and a drain electrode, one of which partially covers the portion of the doped active layer with a larger thickness; conducting an etching process on the doped active layer and the active layer in a region between the source electrode and the drain electrode, forming an optimized channel. With the manufacturing method, the on-state current of a channel of a thin film transistor can be raised.

Claims

1. A manufacturing method of a pixel array structure, comprising:

forming a doped active layer on an active layer, the doped active layer comprising a portion having a first thickness and a portion having a second thickness, wherein the second thickness is less than the first thickness;

forming a source/drain metal layer on the doped active layer and the active layer;

conducting an etching process on the source/drain metal layer, so as to form a source electrode and a drain electrode, one of which partially covers the portion of the doped active layer having the first thickness; and

conducting an etching process on the doped active layer and the active layer between the source electrode and the drain electrode, so as to form a channel located between a remaining portion of the doped active layer having the first thickness and the other of the source electrode and the drain electrode,

wherein the doped active layer and the active layer between the source electrode and the drain electrode are etched in a same process, until the portion of the doped active layer having the second thickness is removed.

2. The manufacturing method of the pixel array structure claimed as claim 1, wherein the first thickness of the doped active layer is 4 to 7 times a thickness of the active layer.

3. The manufacturing method of the pixel array structure claimed as claim 2, wherein the first thickness of the doped active layer is 5 times the thickness of the active layer.

4. The manufacturing method of the pixel array structure claimed as claim 1, wherein a width of the channel is in a range of 1 to 3 micrometers.

5. The manufacturing method of the pixel array structure claimed as claim 1, wherein with a half-tone or gray-tone mask, the doped active layer comprising the portion having the first thickness is formed on the active layer.

6. The manufacturing method of the pixel array structure claimed as claim 1, wherein before formation of the doped active layer over the active layer, the method further comprises:

producing a gate electrode and a gate insulating layer on a base substrate; and

forming the active layer on the gate insulating layer, and conducting an etching process on the active layer to remove the active layer in areas outside of where the gate electrode is located.

7. The manufacturing method of the pixel array structure claimed as claim 5, wherein the source electrode partially covers the portion of the doped active layer having the first thickness, and wherein before formation of the source/drain metal layer, the method further comprises:

forming a first pixel electrode layer, and allowing the first pixel electrode layer to cover the active layer incompletely, and to cover a gate insulating layer uncovered by the active layer.

11. The manufacturing method of the pixel array structure claimed as claim 6, wherein the source electrode partially covers the portion of the doped active layer having the first thickness, and wherein, before formation of the source/drain metal layer, the method further comprises:

forming a first pixel electrode layer, and allowing the first pixel electrode layer to cover the active layer incompletely, and to cover the gate insulating layer uncovered by the active layer.

8. A pixel array structure, comprising:

a base substrate and a gate electrode formed on the base substrate;

a gate insulating layer, an active layer and a doped active layer formed on the gate electrode in sequence, the doped active layer comprising a portion having a first thickness and a portion having a second thickness, wherein the second thickness is less than the first thickness; and

a source/drain electrode layer formed over the doped active layer, wherein the source/drain electrode layer comprises a source electrode and a drain electrode,

wherein only one electrode of the source electrode and the drain electrode partially covers the portion of the doped active layer having the first thickness, and a channel is provided between a doped active layer retained between the one electrode and the other of the source electrode and the drain electrode.

9. An array substrate, comprising the pixel array structure claimed as claim 8.

10. A display device, comprising an array substrate claimed as claim 9 and a counter substrate.

12. A manufacturing method of a pixel array structure, comprising:

forming a doped active layer on an active layer, the doped active layer comprising a portion having a first thickness and a portion having a second thickness, wherein the second thickness is less than the first thickness;

forming a source/drain metal layer on the doped active layer and the active layer;

conducting an etching process on the source/drain metal layer, so as to form a source electrode and a drain electrode, one of which partially covers the portion of the doped active layer having the first thickness;

conducting an etching process on the doped active layer and the active layer between the source electrode and the drain electrode, so as to form a channel located between a remaining portion of the doped active layer having the first thickness and the other of the source electrode and the drain electrode;

wherein before formation of the doped active layer over the active layer, the method further comprises;

producing a gate electrode and a gate insulating layer on a base substrate; and

forming the active layer on the gate insulating layer, and conducting an etching process on the active layer to remove the active layer in areas outside of where the gate electrode is located.